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Add patterns for SHLD64* and SHRD64*.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41975 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -338,7 +338,9 @@ MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const {
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case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
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case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
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case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
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case X86::SHLD32rri8:{// A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
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case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
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case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
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case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
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unsigned Opc;
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unsigned Size;
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switch (MI->getOpcode()) {
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@ -347,6 +349,8 @@ MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const {
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case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
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case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
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case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
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case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
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case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
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}
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unsigned Amt = MI->getOperand(3).getImmedValue();
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unsigned A = MI->getOperand(0).getReg();
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@ -564,38 +564,50 @@ def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
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let isTwoAddress = 1 in {
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let Uses = [CL] in {
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def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
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"shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}", []>, TB;
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"shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
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[(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))]>, TB;
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def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
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"shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}", []>, TB;
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"shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
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[(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))]>, TB;
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}
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let isCommutable = 1 in { // FIXME: Update X86InstrInfo::commuteInstruction
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def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
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(outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3),
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"shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
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TB;
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"shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
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[(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2,
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(i8 imm:$src3)))]>,
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TB;
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def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
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(outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3),
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"shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
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"shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
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[(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2,
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(i8 imm:$src3)))]>,
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TB;
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} // isCommutable
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} // isTwoAddress
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// Temporary hack: there is no patterns associated with these instructions
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// so we have to tell tblgen that these do not produce results.
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let Uses = [CL] in {
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def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
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"shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}", []>, TB;
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"shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
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[(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL),
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addr:$dst)]>, TB;
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def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
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"shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}", []>, TB;
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"shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
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[(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL),
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addr:$dst)]>, TB;
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}
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def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
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(outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
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"shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
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"shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
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[(store (X86shld (loadi64 addr:$dst), GR64:$src2,
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(i8 imm:$src3)), addr:$dst)]>,
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TB;
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def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
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(outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
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"shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
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"shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
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[(store (X86shrd (loadi64 addr:$dst), GR64:$src2,
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(i8 imm:$src3)), addr:$dst)]>,
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TB;
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} // Defs = [EFLAGS]
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