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Don't cache the instruction and register info from the TargetMachine, because

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the internals of TargetMachine could change.

No functionality change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183572 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling
2013-06-07 21:04:35 +00:00
parent a5e5ba611f
commit e488b4ecdc
3 changed files with 6 additions and 6 deletions
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6
lib/Target/XCore/XCoreRegisterInfo.cpp
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@@ -37,8 +37,8 @@
using namespace llvm;
XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii)
: XCoreGenRegisterInfo(XCore::LR), TII(tii) {
XCoreRegisterInfo::XCoreRegisterInfo()
: XCoreGenRegisterInfo(XCore::LR) {
}
// helper functions
@@ -112,6 +112,7 @@ XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
int FrameIndex = FrameOp.getIndex();
MachineFunction &MF = *MI.getParent()->getParent();
const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
int StackSize = MF.getFrameInfo()->getStackSize();
@@ -249,6 +250,7 @@ loadConstant(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
report_fatal_error("loadConstant value too big " + Twine(Value));
}
int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
const TargetInstrInfo &TII = *MBB.getParent()->getTarget().getInstrInfo();
BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value);
}