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Fix a performance regression from r144565. Positive offsets were being lowered
into registers, rather then encoded directly in the load/store. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144576 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -874,9 +874,9 @@ void ARMFastISel::ARMSimplifyAddress(Address &Addr, EVT VT, bool useAM3) {
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// Integer loads/stores handle 12-bit offsets.
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needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
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// Handle negative offsets.
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if (isThumb2)
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needsLowering = !(needsLowering && Subtarget->hasV6T2Ops() &&
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Addr.Offset < 0 && Addr.Offset > -256);
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if (needsLowering && isThumb2)
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needsLowering = !(Subtarget->hasV6T2Ops() && Addr.Offset < 0 &&
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Addr.Offset > -256);
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} else {
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// ARM halfword load/stores and signed byte loads use +/-imm8 offsets.
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needsLowering = (Addr.Offset > 255 || Addr.Offset < -255);
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55
test/CodeGen/ARM/fast-isel-ldr-str-arm.ll
Normal file
55
test/CodeGen/ARM/fast-isel-ldr-str-arm.ll
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@ -0,0 +1,55 @@
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; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=ARM
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define i32 @t1(i32* nocapture %ptr) nounwind readonly {
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entry:
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; ARM: t1
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%add.ptr = getelementptr inbounds i32* %ptr, i32 1
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%0 = load i32* %add.ptr, align 4
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; ARM: ldr r{{[0-9]}}, [r0, #4]
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ret i32 %0
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}
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define i32 @t2(i32* nocapture %ptr) nounwind readonly {
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entry:
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; ARM: t2
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%add.ptr = getelementptr inbounds i32* %ptr, i32 63
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%0 = load i32* %add.ptr, align 4
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; ARM: ldr.w r{{[0-9]}}, [r0, #252]
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ret i32 %0
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}
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define zeroext i16 @t3(i16* nocapture %ptr) nounwind readonly {
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entry:
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; ARM: t3
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%add.ptr = getelementptr inbounds i16* %ptr, i16 1
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%0 = load i16* %add.ptr, align 4
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; ARM: ldrh r{{[0-9]}}, [r0, #2]
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ret i16 %0
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}
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define zeroext i16 @t4(i16* nocapture %ptr) nounwind readonly {
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entry:
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; ARM: t4
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%add.ptr = getelementptr inbounds i16* %ptr, i16 63
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%0 = load i16* %add.ptr, align 4
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; ARM: ldrh.w r{{[0-9]}}, [r0, #126]
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ret i16 %0
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}
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define zeroext i8 @t5(i8* nocapture %ptr) nounwind readonly {
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entry:
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; ARM: t5
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%add.ptr = getelementptr inbounds i8* %ptr, i8 1
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%0 = load i8* %add.ptr, align 4
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; ARM: ldrb r{{[0-9]}}, [r0, #1]
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ret i8 %0
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}
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define zeroext i8 @t6(i8* nocapture %ptr) nounwind readonly {
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entry:
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; ARM: t6
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%add.ptr = getelementptr inbounds i8* %ptr, i8 63
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%0 = load i8* %add.ptr, align 4
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; ARM: ldrb.w r{{[0-9]}}, [r0, #63]
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ret i8 %0
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}
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