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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-12 13:30:51 +00:00
R600/SI: add cummuting of rev instructions
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178127 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Christian Konig
parent
45b14e341a
commit
e49230895d
@ -544,6 +544,13 @@ SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
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unsigned NumDefs = Desc->getNumDefs();
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unsigned NumOps = Desc->getNumOperands();
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// Commuted opcode if available
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int OpcodeRev = Desc->isCommutable() ? TII->commuteOpcode(Opcode) : -1;
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const MCInstrDesc *DescRev = OpcodeRev == -1 ? 0 : &TII->get(OpcodeRev);
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assert(!DescRev || DescRev->getNumDefs() == NumDefs);
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assert(!DescRev || DescRev->getNumOperands() == NumOps);
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// e64 version if available, -1 otherwise
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int OpcodeE64 = AMDGPU::getVOPe64(Opcode);
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const MCInstrDesc *DescE64 = OpcodeE64 == -1 ? 0 : &TII->get(OpcodeE64);
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@ -605,8 +612,7 @@ SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
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continue;
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}
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if (i == 1 && Desc->isCommutable() &&
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fitsRegClass(DAG, Ops[0], RegClass)) {
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if (i == 1 && DescRev && fitsRegClass(DAG, Ops[0], RegClass)) {
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unsigned OtherRegClass = Desc->OpInfo[NumDefs].RegClass;
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assert(isVSrc(OtherRegClass) || isSSrc(OtherRegClass));
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@ -620,6 +626,9 @@ SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
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SDValue Tmp = Ops[1];
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Ops[1] = Ops[0];
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Ops[0] = Tmp;
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Desc = DescRev;
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DescRev = 0;
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continue;
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}
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}
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@ -655,10 +664,7 @@ SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
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for (unsigned i = NumOps - NumDefs, e = Node->getNumOperands(); i < e; ++i)
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Ops.push_back(Node->getOperand(i));
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// Either create a complete new or update the current instruction
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if (Promote2e64)
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return DAG.getMachineNode(OpcodeE64, Node->getDebugLoc(),
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// Create a complete new instruction
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return DAG.getMachineNode(Desc->Opcode, Node->getDebugLoc(),
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Node->getVTList(), Ops.data(), Ops.size());
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else
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return DAG.UpdateNodeOperands(Node, Ops.data(), Ops.size());
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}
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@ -158,6 +158,21 @@ SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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}
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}
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unsigned SIInstrInfo::commuteOpcode(unsigned Opcode) const {
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int NewOpc;
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// Try to map original to commuted opcode
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if ((NewOpc = AMDGPU::getCommuteRev(Opcode)) != -1)
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return NewOpc;
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// Try to map commuted to original opcode
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if ((NewOpc = AMDGPU::getCommuteOrig(Opcode)) != -1)
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return NewOpc;
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return Opcode;
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}
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MachineInstr *SIInstrInfo::commuteInstruction(MachineInstr *MI,
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bool NewMI) const {
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@ -165,7 +180,12 @@ MachineInstr *SIInstrInfo::commuteInstruction(MachineInstr *MI,
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!MI->getOperand(2).isReg())
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return 0;
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return TargetInstrInfo::commuteInstruction(MI, NewMI);
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MI = TargetInstrInfo::commuteInstruction(MI, NewMI);
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if (MI)
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MI->setDesc(get(commuteOpcode(MI->getOpcode())));
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return MI;
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}
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MachineInstr * SIInstrInfo::getMovImmInstr(MachineFunction *MF, unsigned DstReg,
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@ -35,6 +35,8 @@ public:
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const;
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unsigned commuteOpcode(unsigned Opcode) const;
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virtual MachineInstr *commuteInstruction(MachineInstr *MI,
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bool NewMI=false) const;
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@ -76,6 +78,8 @@ public:
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namespace AMDGPU {
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int getVOPe64(uint16_t Opcode);
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int getCommuteRev(uint16_t Opcode);
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int getCommuteOrig(uint16_t Opcode);
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} // End namespace AMDGPU
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@ -138,6 +138,11 @@ class VOP <string opName> {
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string OpName = opName;
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}
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class VOP2_REV <string revOp, bit isOrig> {
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string RevOp = revOp;
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bit IsOrig = isOrig;
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}
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multiclass VOP1_Helper <bits<8> op, RegisterClass drc, RegisterClass src,
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string opName, list<dag> pattern> {
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@ -166,11 +171,11 @@ multiclass VOP1_64 <bits<8> op, string opName, list<dag> pattern>
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: VOP1_Helper <op, VReg_64, VSrc_64, opName, pattern>;
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multiclass VOP2_Helper <bits<6> op, RegisterClass vrc, RegisterClass arc,
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string opName, list<dag> pattern> {
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string opName, list<dag> pattern, string revOp> {
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def _e32 : VOP2 <
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op, (outs vrc:$dst), (ins arc:$src0, vrc:$src1),
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opName#"_e32 $dst, $src0, $src1", pattern
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>, VOP <opName>;
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>, VOP <opName>, VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
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def _e64 : VOP3 <
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{1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
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@ -179,23 +184,26 @@ multiclass VOP2_Helper <bits<6> op, RegisterClass vrc, RegisterClass arc,
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i32imm:$abs, i32imm:$clamp,
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i32imm:$omod, i32imm:$neg),
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opName#"_e64 $dst, $src0, $src1, $abs, $clamp, $omod, $neg", []
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>, VOP <opName> {
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>, VOP <opName>, VOP2_REV<revOp#"_e64", !eq(revOp, opName)> {
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let SRC2 = SIOperand.ZERO;
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}
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}
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multiclass VOP2_32 <bits<6> op, string opName, list<dag> pattern>
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: VOP2_Helper <op, VReg_32, VSrc_32, opName, pattern>;
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multiclass VOP2_32 <bits<6> op, string opName, list<dag> pattern,
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string revOp = opName>
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: VOP2_Helper <op, VReg_32, VSrc_32, opName, pattern, revOp>;
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multiclass VOP2_64 <bits<6> op, string opName, list<dag> pattern>
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: VOP2_Helper <op, VReg_64, VSrc_64, opName, pattern>;
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multiclass VOP2_64 <bits<6> op, string opName, list<dag> pattern,
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string revOp = opName>
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: VOP2_Helper <op, VReg_64, VSrc_64, opName, pattern, revOp>;
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multiclass VOP2b_32 <bits<6> op, string opName, list<dag> pattern> {
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multiclass VOP2b_32 <bits<6> op, string opName, list<dag> pattern,
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string revOp = opName> {
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def _e32 : VOP2 <
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op, (outs VReg_32:$dst), (ins VSrc_32:$src0, VReg_32:$src1),
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opName#"_e32 $dst, $src0, $src1", pattern
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>, VOP <opName>;
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>, VOP <opName>, VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
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def _e64 : VOP3b <
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{1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
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@ -204,7 +212,7 @@ multiclass VOP2b_32 <bits<6> op, string opName, list<dag> pattern> {
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i32imm:$abs, i32imm:$clamp,
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i32imm:$omod, i32imm:$neg),
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opName#"_e64 $dst, $src0, $src1, $abs, $clamp, $omod, $neg", []
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>, VOP <opName> {
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>, VOP <opName>, VOP2_REV<revOp#"_e64", !eq(revOp, opName)> {
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let SRC2 = SIOperand.ZERO;
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/* the VOP2 variant puts the carry out into VCC, the VOP3 variant
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can write it into any SGPR. We currently don't use the carry out,
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@ -327,4 +335,22 @@ def getVOPe64 : InstrMapping {
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let ValueCols = [["8"]];
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}
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// Maps an original opcode to its commuted version
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def getCommuteRev : InstrMapping {
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let FilterClass = "VOP2_REV";
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let RowFields = ["RevOp"];
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let ColFields = ["IsOrig"];
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let KeyCol = ["1"];
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let ValueCols = [["0"]];
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}
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// Maps an commuted opcode to its original version
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def getCommuteOrig : InstrMapping {
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let FilterClass = "VOP2_REV";
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let RowFields = ["RevOp"];
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let ColFields = ["IsOrig"];
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let KeyCol = ["0"];
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let ValueCols = [["1"]];
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}
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include "SIInstructions.td"
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@ -804,13 +804,13 @@ let isCommutable = 1 in {
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defm V_ADD_F32 : VOP2_32 <0x00000003, "V_ADD_F32",
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[(set VReg_32:$dst, (fadd VSrc_32:$src0, VReg_32:$src1))]
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>;
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} // End isCommutable = 1
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defm V_SUB_F32 : VOP2_32 <0x00000004, "V_SUB_F32",
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[(set VReg_32:$dst, (fsub VSrc_32:$src0, VReg_32:$src1))]
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>;
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defm V_SUBREV_F32 : VOP2_32 <0x00000005, "V_SUBREV_F32", [], "V_SUB_F32">;
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} // End isCommutable = 1
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defm V_SUBREV_F32 : VOP2_32 <0x00000005, "V_SUBREV_F32", []>;
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defm V_MAC_LEGACY_F32 : VOP2_32 <0x00000006, "V_MAC_LEGACY_F32", []>;
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let isCommutable = 1 in {
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@ -848,22 +848,20 @@ defm V_MAX_I32 : VOP2_32 <0x00000012, "V_MAX_I32", []>;
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defm V_MIN_U32 : VOP2_32 <0x00000013, "V_MIN_U32", []>;
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defm V_MAX_U32 : VOP2_32 <0x00000014, "V_MAX_U32", []>;
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} // End isCommutable = 1
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defm V_LSHR_B32 : VOP2_32 <0x00000015, "V_LSHR_B32",
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[(set VReg_32:$dst, (srl VSrc_32:$src0, (i32 VReg_32:$src1)))]
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>;
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defm V_LSHRREV_B32 : VOP2_32 <0x00000016, "V_LSHRREV_B32", []>;
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defm V_LSHRREV_B32 : VOP2_32 <0x00000016, "V_LSHRREV_B32", [], "V_LSHR_B32">;
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defm V_ASHR_I32 : VOP2_32 <0x00000017, "V_ASHR_I32",
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[(set VReg_32:$dst, (sra VSrc_32:$src0, (i32 VReg_32:$src1)))]
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>;
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defm V_ASHRREV_I32 : VOP2_32 <0x00000018, "V_ASHRREV_I32", []>;
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defm V_ASHRREV_I32 : VOP2_32 <0x00000018, "V_ASHRREV_I32", [], "V_ASHR_I32">;
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defm V_LSHL_B32 : VOP2_32 <0x00000019, "V_LSHL_B32",
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[(set VReg_32:$dst, (shl VSrc_32:$src0, (i32 VReg_32:$src1)))]
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>;
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defm V_LSHLREV_B32 : VOP2_32 <0x0000001a, "V_LSHLREV_B32", []>;
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let isCommutable = 1 in {
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defm V_LSHLREV_B32 : VOP2_32 <0x0000001a, "V_LSHLREV_B32", [], "V_LSHL_B32">;
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defm V_AND_B32 : VOP2_32 <0x0000001b, "V_AND_B32",
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[(set VReg_32:$dst, (and VSrc_32:$src0, VReg_32:$src1))]
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@ -884,25 +882,24 @@ defm V_MADAK_F32 : VOP2_32 <0x00000021, "V_MADAK_F32", []>;
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//defm V_BCNT_U32_B32 : VOP2_32 <0x00000022, "V_BCNT_U32_B32", []>;
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//defm V_MBCNT_LO_U32_B32 : VOP2_32 <0x00000023, "V_MBCNT_LO_U32_B32", []>;
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//defm V_MBCNT_HI_U32_B32 : VOP2_32 <0x00000024, "V_MBCNT_HI_U32_B32", []>;
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let Defs = [VCC] in { // Carry-out goes to VCC
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let isCommutable = 1 in {
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let isCommutable = 1, Defs = [VCC] in { // Carry-out goes to VCC
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defm V_ADD_I32 : VOP2b_32 <0x00000025, "V_ADD_I32",
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[(set VReg_32:$dst, (add (i32 VSrc_32:$src0), (i32 VReg_32:$src1)))]
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>;
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} // End isCommutable = 1
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defm V_SUB_I32 : VOP2b_32 <0x00000026, "V_SUB_I32",
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[(set VReg_32:$dst, (sub (i32 VSrc_32:$src0), (i32 VReg_32:$src1)))]
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>;
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defm V_SUBREV_I32 : VOP2b_32 <0x00000027, "V_SUBREV_I32", [], "V_SUB_I32">;
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defm V_SUBREV_I32 : VOP2b_32 <0x00000027, "V_SUBREV_I32", []>;
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let Uses = [VCC] in { // Carry-out comes from VCC
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defm V_ADDC_U32 : VOP2b_32 <0x00000028, "V_ADDC_U32", []>;
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defm V_SUBB_U32 : VOP2b_32 <0x00000029, "V_SUBB_U32", []>;
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defm V_SUBBREV_U32 : VOP2b_32 <0x0000002a, "V_SUBBREV_U32", []>;
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defm V_SUBBREV_U32 : VOP2b_32 <0x0000002a, "V_SUBBREV_U32", [], "V_SUBB_U32">;
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} // End Uses = [VCC]
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} // End Defs = [VCC]
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} // End isCommutable = 1, Defs = [VCC]
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defm V_LDEXP_F32 : VOP2_32 <0x0000002b, "V_LDEXP_F32", []>;
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////def V_CVT_PKACCUM_U8_F32 : VOP2_U8 <0x0000002c, "V_CVT_PKACCUM_U8_F32", []>;
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////def V_CVT_PKNORM_I16_F32 : VOP2_I16 <0x0000002d, "V_CVT_PKNORM_I16_F32", []>;
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@ -1,6 +1,6 @@
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;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
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;CHECK: V_LSHL_B32_e64 VGPR0, VGPR0, 1, 0, 0, 0, 0
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;CHECK: V_LSHLREV_B32_e32 VGPR0, 1, VGPR0
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define void @test(i32 %p) {
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%i = mul i32 %p, 2
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@ -1,6 +1,6 @@
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;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
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;CHECK: V_LSHR_B32_e64 VGPR0, VGPR0, 1, 0, 0, 0, 0
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;CHECK: V_LSHRREV_B32_e32 VGPR0, 1, VGPR0
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define void @test(i32 %p) {
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%i = udiv i32 %p, 2
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@ -2,7 +2,7 @@
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;CHECK: V_MOV_B32_e32 VGPR1, -1431655765
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;CHECK-NEXT: V_MUL_HI_U32 VGPR0, VGPR0, VGPR1, 0, 0, 0, 0, 0
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;CHECK-NEXT: V_LSHR_B32_e64 VGPR0, VGPR0, 1, 0, 0, 0, 0
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;CHECK-NEXT: V_LSHRREV_B32_e32 VGPR0, 1, VGPR0
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define void @test(i32 %p) {
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%i = udiv i32 %p, 3
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