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Rename SelectShifterOperand to SelectThumb2ShifterOperandReg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73975 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -92,8 +92,8 @@ public:
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bool SelectThumbAddrModeSP(SDValue Op, SDValue N, SDValue &Base,
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SDValue &OffImm);
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bool SelectShifterOperand(SDValue Op, SDValue N,
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SDValue &BaseReg, SDValue &Opc);
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bool SelectThumb2ShifterOperandReg(SDValue Op, SDValue N,
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SDValue &BaseReg, SDValue &Opc);
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bool SelectShifterOperandReg(SDValue Op, SDValue N, SDValue &A,
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SDValue &B, SDValue &C);
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@ -520,10 +520,10 @@ bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue Op, SDValue N,
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return false;
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}
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bool ARMDAGToDAGISel::SelectShifterOperand(SDValue Op,
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SDValue N,
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SDValue &BaseReg,
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SDValue &Opc) {
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bool ARMDAGToDAGISel::SelectThumb2ShifterOperandReg(SDValue Op,
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SDValue N,
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SDValue &BaseReg,
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SDValue &Opc) {
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ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
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// Don't match base register only case. That is matched to a separate
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@ -14,7 +14,7 @@
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// Shifted operands. No register controlled shifts for Thumb2.
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// Note: We do not support rrx shifted operands yet.
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def t2_so_reg : Operand<i32>, // reg imm
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ComplexPattern<i32, 2, "SelectShifterOperand",
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ComplexPattern<i32, 2, "SelectThumb2ShifterOperandReg",
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[shl,srl,sra,rotr]> {
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let PrintMethod = "printSOOperand";
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let MIOperandInfo = (ops GPR, i32imm);
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