From e4f17a5f9b6b5c94dccfd14babcf58d9d5dab4e8 Mon Sep 17 00:00:00 2001 From: Nate Begeman Date: Wed, 23 Nov 2005 05:29:52 +0000 Subject: [PATCH] Some first bits of AltiVec stuff: Instruction Formats, Encodings, and Registers. Apologies to Jim if the scheduling info so far isn't accurate. There's a few more things like VRsave support that need to be finished up in my local tree before I can commit code that Does The Right Thing for turning 4 x float into the various altivec packed float instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24489 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCInstrFormats.td | 45 ++++++++++++++++++++++++ lib/Target/PowerPC/PPCInstrInfo.td | 49 +++++++++++++++++++++++++++ lib/Target/PowerPC/PPCRegisterInfo.td | 30 +++++++++++++++- 3 files changed, 123 insertions(+), 1 deletion(-) diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td index 2ec71532d80..8f93ac9fd3f 100644 --- a/lib/Target/PowerPC/PPCInstrFormats.td +++ b/lib/Target/PowerPC/PPCInstrFormats.td @@ -548,6 +548,51 @@ class MDForm_1 opcode, bits<3> xo, dag OL, string asmstr, let Inst{31} = RC; } +// E-1 VA-Form +class VAForm_1 xo, dag OL, string asmstr, + InstrItinClass itin, list pattern> + : I<4, OL, asmstr, itin> { + bits<5> VD; + bits<5> VA; + bits<5> VB; + bits<5> VC; + + let Inst{6-10} = VD; + let Inst{11-15} = VA; + let Inst{16-20} = VB; + let Inst{21-25} = VC; + let Inst{26-31} = xo; +} + +// E-2 VX-Form +class VXForm_1 xo, dag OL, string asmstr, + InstrItinClass itin, list pattern> + : I<4, OL, asmstr, itin> { + bits<5> VD; + bits<5> VA; + bits<5> VB; + + let Inst{6-10} = VD; + let Inst{11-15} = VA; + let Inst{16-20} = VB; + let Inst{21-31} = xo; +} + +// E-4 VXR-Form +class VXRForm_1 xo, bit rc, dag OL, string asmstr, + InstrItinClass itin, list pattern> + : I<4, OL, asmstr, itin> { + bits<5> VD; + bits<5> VA; + bits<5> VB; + + let Inst{6-10} = VD; + let Inst{11-15} = VA; + let Inst{16-20} = VB; + let Inst{21} = rc; + let Inst{22-31} = xo; +} + //===----------------------------------------------------------------------===// def NoItin : InstrItinClass; class Pseudo pattern> diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index 7e09b4d6df4..af6fb0d2853 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -360,6 +360,18 @@ def LWZX : XForm_1<31, 23, (ops GPRC:$dst, GPRC:$base, GPRC:$index), "lwzx $dst, $base, $index", LdStGeneral>; def LDX : XForm_1<31, 21, (ops GPRC:$dst, GPRC:$base, GPRC:$index), "ldx $dst, $base, $index", LdStLD>, isPPC64; +def LVEBX: XForm_1<31, 7, (ops VRRC:$vD, GPRC:$base, GPRC:$rA), + "lvebx $vD, $base, $rA", LdStGeneral>; +def LVEHX: XForm_1<31, 39, (ops VRRC:$vD, GPRC:$base, GPRC:$rA), + "lvehx $vD, $base, $rA", LdStGeneral>; +def LVEWX: XForm_1<31, 71, (ops VRRC:$vD, GPRC:$base, GPRC:$rA), + "lvewx $vD, $base, $rA", LdStGeneral>; +def LVX : XForm_1<31, 103, (ops VRRC:$vD, GPRC:$base, GPRC:$rA), + "lvx $vD, $base, $rA", LdStGeneral>; +def LVSL : XForm_1<31, 6, (ops VRRC:$vD, GPRC:$base, GPRC:$rA), + "lvsl $vD, $base, $rA", LdStGeneral>; +def LVSR : XForm_1<31, 38, (ops VRRC:$vD, GPRC:$base, GPRC:$rA), + "lvsl $vD, $base, $rA", LdStGeneral>; } def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), "nand $rA, $rS, $rB", IntGeneral, @@ -431,6 +443,14 @@ def STDX : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB), "stdx $rS, $rA, $rB", LdStSTD>, isPPC64; def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB), "stdux $rS, $rA, $rB", LdStSTD>, isPPC64; +def STVEBX: XForm_8<31, 135, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB), + "stvebx $rS, $rA, $rB", LdStGeneral>; +def STVEHX: XForm_8<31, 167, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB), + "stvehx $rS, $rA, $rB", LdStGeneral>; +def STVEWX: XForm_8<31, 199, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB), + "stvewx $rS, $rA, $rB", LdStGeneral>; +def STVX : XForm_8<31, 231, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB), + "stvx $rS, $rA, $rB", LdStGeneral>; } def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH), "srawi $rA, $rS, $SH", IntShift, @@ -746,6 +766,35 @@ def RLDICR : MDForm_1<30, 1, "rldicr $rA, $rS, $SH, $ME", IntRotateD, []>, isPPC64; +// VA-Form instructions. 3-input AltiVec ops. +def VMADDFP: VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC), + "vmaddfp $vD, $vA, $vB, $vC", VecFP, + []>; + +// VX-Form instructions. AltiVec arithmetic ops. +def VADDFP : VXForm_1<10, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), + "vaddfp $vD, $vA, $vB", VecFP, + []>; +def VADDUWM: VXForm_1<128, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), + "vadduwm $vD, $vA, $vB", VecGeneral, + []>; +def VAND : VXForm_1<1028, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), + "vand $vD, $vA, $vB", VecGeneral, + []>; +def VCFSX : VXForm_1<842, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), + "vcfsx $vD, $vB, $UIMM", VecFP, + []>; +def VCFUX : VXForm_1<778, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), + "vcfux $vD, $vB, $UIMM", VecFP, + []>; +def VOR : VXForm_1<1156, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), + "vor $vD, $vA, $vB", VecGeneral, + []>; +def VXOR : VXForm_1<1220, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), + "vxor $vD, $vA, $vB", VecGeneral, + []>; + + //===----------------------------------------------------------------------===// // PowerPC Instruction Patterns // diff --git a/lib/Target/PowerPC/PPCRegisterInfo.td b/lib/Target/PowerPC/PPCRegisterInfo.td index 2ddbb7c92d3..c3fa558cc8c 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.td +++ b/lib/Target/PowerPC/PPCRegisterInfo.td @@ -37,6 +37,11 @@ class FPR num, string n> : PPCReg { field bits<5> Num = num; } +// VR - One of the 32 128-bit vector registers +class VR num, string n> : PPCReg { + field bits<5> Num = num; +} + // CR - One of the 8 4-bit condition registers class CR num, string n> : PPCReg { field bits<5> Num = num; @@ -96,6 +101,23 @@ def F26 : FPR<26, "f26">; def F27 : FPR<27, "f27">; def F28 : FPR<28, "f28">; def F29 : FPR<29, "f29">; def F30 : FPR<30, "f30">; def F31 : FPR<31, "f31">; +// Floating-point registers +def V0 : VR< 0, "v0">; def V1 : VR< 1, "v1">; +def V2 : VR< 2, "v2">; def V3 : VR< 3, "v3">; +def V4 : VR< 4, "v4">; def V5 : VR< 5, "v5">; +def V6 : VR< 6, "v6">; def V7 : VR< 7, "v7">; +def V8 : VR< 8, "v8">; def V9 : VR< 9, "v9">; +def V10 : VR<10, "v10">; def V11 : VR<11, "v11">; +def V12 : VR<12, "v12">; def V13 : VR<13, "v13">; +def V14 : VR<14, "v14">; def V15 : VR<15, "v15">; +def V16 : VR<16, "v16">; def V17 : VR<17, "v17">; +def V18 : VR<18, "v18">; def V19 : VR<19, "v19">; +def V20 : VR<20, "v20">; def V21 : VR<21, "v21">; +def V22 : VR<22, "v22">; def V23 : VR<23, "v23">; +def V24 : VR<24, "v24">; def V25 : VR<25, "v25">; +def V26 : VR<26, "v26">; def V27 : VR<27, "v27">; +def V28 : VR<28, "v28">; def V29 : VR<29, "v29">; +def V30 : VR<30, "v30">; def V31 : VR<31, "v31">; // Condition registers def CR0 : CR<0, "cr0">; def CR1 : CR<1, "cr1">; @@ -104,9 +126,12 @@ def CR4 : CR<4, "cr4">; def CR5 : CR<5, "cr5">; def CR6 : CR<6, "cr6">; def CR7 : CR<7, "cr7">; // Link register -def LR : SPR<2, "lr">; +// FIXME: encode actual spr numbers here +def LR : SPR<2, "lr">; // Count register def CTR : SPR<3, "ctr">; +// VRsave register +def VRSAVE: SPR<4, "VRsave">; /// Register classes // Allocate volatiles first @@ -167,5 +192,8 @@ def F4RC : RegisterClass<"PPC", f32, 32, [F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>; +def VRRC : RegisterClass<"PPC", i128, 128, [V0, V1, V2, V3, V4, V5, V6, V7, V8, + V9, V10, V11, V12, V13, V14, V15, V16, V17, V18, V19, V20, V21, V22, V23, + V24, V25, V26, V27, V28, V29, V30, V31]>; def CRRC : RegisterClass<"PPC", i32, 32, [CR0, CR1, CR5, CR6, CR7, CR2, CR3, CR4]>;