6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-15 20:29:48 +00:00
Code Issues Projects Releases Wiki Activity

- Enable x86 isel preprocessing by default unless -fast is specified.

Browse Source 
- Also disable isel load folding if -fast.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29956 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2006-08-29 18:28:33 +00:00
parent 718996654b
commit e50794adda
3 changed files with 13 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/Target/X86/X86.h
View File

@ -28,7 +28,7 @@ class MachineCodeEmitter;
/// createX86ISelDag - This pass converts a legalized DAG into a
/// X86-specific DAG, ready for instruction scheduling.
///
FunctionPass *createX86ISelDag(X86TargetMachine &TM);
FunctionPass *createX86ISelDag(X86TargetMachine &TM, bool Fast);
/// createX86FloatingPointStackifierPass - This function returns a pass which
/// converts floating point register references and pseudo instructions into

15
lib/Target/X86/X86ISelDAGToDAG.cpp
View File

@ -92,6 +92,10 @@ namespace {
/// register should set this to true.
bool ContainsFPCode;
/// FastISel - Enable fast(er) instruction selection.
///
bool FastISel;
/// X86Lowering - This object fully describes how to lower LLVM code to an
/// X86-specific SelectionDAG.
X86TargetLowering X86Lowering;
@ -103,8 +107,9 @@ namespace {
unsigned GlobalBaseReg;
public:
X86DAGToDAGISel(X86TargetMachine &TM)
X86DAGToDAGISel(X86TargetMachine &TM, bool fast)
: SelectionDAGISel(X86Lowering),
ContainsFPCode(false), FastISel(fast),
X86Lowering(*TM.getTargetLowering()),
Subtarget(&TM.getSubtarget<X86Subtarget>()) {}
@ -237,7 +242,7 @@ bool X86DAGToDAGISel::CanBeFoldedBy(SDNode *N, SDNode *U) {
// / [X]
// | ^
// [U]--------|
return !isNonImmUse(U, N);
return !FastISel && !isNonImmUse(U, N);
}
/// MoveBelowTokenFactor - Replace TokenFactor operand with load's chain operand
@ -370,7 +375,7 @@ void X86DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
DEBUG(BB->dump());
MachineFunction::iterator FirstMBB = BB;
if (X86ISelPreproc)
if (!FastISel)
InstructionSelectPreprocess(DAG);
// Codegen the basic block.
@ -1071,6 +1076,6 @@ SelectInlineAsmMemoryOperand(const SDOperand &Op, char ConstraintCode,
/// createX86ISelDag - This pass converts a legalized DAG into a
/// X86-specific DAG, ready for instruction scheduling.
///
FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM) {
return new X86DAGToDAGISel(TM);
FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM, bool Fast) {
return new X86DAGToDAGISel(TM, Fast);
}

4
lib/Target/X86/X86TargetMachine.cpp
View File

@ -103,7 +103,7 @@ bool X86TargetMachine::addPassesToEmitFile(PassManager &PM, std::ostream &Out,
PM.add(createUnreachableBlockEliminationPass());
// Install an instruction selector.
PM.add(createX86ISelDag(*this));
PM.add(createX86ISelDag(*this, Fast));
// Print the instruction selected machine code...
if (PrintMachineCode)
@ -168,7 +168,7 @@ void X86JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
PM.add(createUnreachableBlockEliminationPass());
// Install an instruction selector.
PM.add(createX86ISelDag(TM));
PM.add(createX86ISelDag(TM, false));
// Print the instruction selected machine code...
if (PrintMachineCode)