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Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson
2009-08-10 22:56:29 +00:00
parent a8c6908995
commit e50ed30282
104 changed files with 7032 additions and 7032 deletions
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54
lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
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@@ -107,19 +107,19 @@ namespace {
/// getI8Imm - Return a target constant with the specified value, of type
/// i8.
inline SDValue getI8Imm(uint64_t Imm) {
return CurDAG->getTargetConstant(Imm, MVT::i8);
return CurDAG->getTargetConstant(Imm, EVT::i8);
}
/// getI16Imm - Return a target constant with the specified value, of type
/// i16.
inline SDValue getI16Imm(uint64_t Imm) {
return CurDAG->getTargetConstant(Imm, MVT::i16);
return CurDAG->getTargetConstant(Imm, EVT::i16);
}
/// getI32Imm - Return a target constant with the specified value, of type
/// i32.
inline SDValue getI32Imm(uint64_t Imm) {
return CurDAG->getTargetConstant(Imm, MVT::i32);
return CurDAG->getTargetConstant(Imm, EVT::i32);
}
// Include the pieces autogenerated from the target description.
@@ -353,7 +353,7 @@ void SystemZDAGToDAGISel::getAddressOperandsRI(const SystemZRRIAddressMode &AM,
Base = AM.Base.Reg;
else
Base = CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, TLI.getPointerTy());
Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i64);
Disp = CurDAG->getTargetConstant(AM.Disp, EVT::i64);
}
void SystemZDAGToDAGISel::getAddressOperands(const SystemZRRIAddressMode &AM,
@@ -405,7 +405,7 @@ bool SystemZDAGToDAGISel::SelectAddrRI12(SDValue Op, SDValue& Addr,
DOUT << "MatchAddress (final): "; DEBUG(AM12.dump());
MVT VT = Addr.getValueType();
EVT VT = Addr.getValueType();
if (AM12.BaseType == SystemZRRIAddressMode::RegBase) {
if (!AM12.Base.Reg.getNode())
AM12.Base.Reg = CurDAG->getRegister(0, VT);
@@ -448,7 +448,7 @@ bool SystemZDAGToDAGISel::SelectAddrRI(SDValue Op, SDValue& Addr,
DOUT << "MatchAddress (final): "; DEBUG(AM.dump());
MVT VT = Addr.getValueType();
EVT VT = Addr.getValueType();
if (AM.BaseType == SystemZRRIAddressMode::RegBase) {
if (!AM.Base.Reg.getNode())
AM.Base.Reg = CurDAG->getRegister(0, VT);
@@ -496,7 +496,7 @@ bool SystemZDAGToDAGISel::SelectAddrRRI12(SDValue Op, SDValue Addr,
DOUT << "MatchAddress (final): "; DEBUG(AM12.dump());
MVT VT = Addr.getValueType();
EVT VT = Addr.getValueType();
if (AM12.BaseType == SystemZRRIAddressMode::RegBase) {
if (!AM12.Base.Reg.getNode())
AM12.Base.Reg = CurDAG->getRegister(0, VT);
@@ -540,7 +540,7 @@ bool SystemZDAGToDAGISel::SelectAddrRRI20(SDValue Op, SDValue Addr,
DOUT << "MatchAddress (final): "; DEBUG(AM.dump());
MVT VT = Addr.getValueType();
EVT VT = Addr.getValueType();
if (AM.BaseType == SystemZRRIAddressMode::RegBase) {
if (!AM.Base.Reg.getNode())
AM.Base.Reg = CurDAG->getRegister(0, VT);
@@ -563,7 +563,7 @@ bool SystemZDAGToDAGISel::SelectLAAddr(SDValue Op, SDValue Addr,
if (MatchAddress(Addr, AM, false))
return false;
MVT VT = Addr.getValueType();
EVT VT = Addr.getValueType();
unsigned Complexity = 0;
if (AM.BaseType == SystemZRRIAddressMode::RegBase)
if (AM.Base.Reg.getNode())
@@ -618,7 +618,7 @@ void SystemZDAGToDAGISel::InstructionSelect() {
SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
SDNode *Node = Op.getNode();
MVT NVT = Node->getValueType(0);
EVT NVT = Node->getValueType(0);
DebugLoc dl = Op.getDebugLoc();
unsigned Opcode = Node->getOpcode();
@@ -648,18 +648,18 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
SDValue N0 = Node->getOperand(0);
SDValue N1 = Node->getOperand(1);
MVT ResVT;
EVT ResVT;
bool is32Bit = false;
switch (NVT.getSimpleVT()) {
default: assert(0 && "Unsupported VT!");
case MVT::i32:
case EVT::i32:
Opc = SystemZ::SDIVREM32r; MOpc = SystemZ::SDIVREM32m;
ResVT = MVT::v2i64;
ResVT = EVT::v2i64;
is32Bit = true;
break;
case MVT::i64:
case EVT::i64:
Opc = SystemZ::SDIVREM64r; MOpc = SystemZ::SDIVREM64m;
ResVT = MVT::v2i64;
ResVT = EVT::v2i64;
break;
}
@@ -669,7 +669,7 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
// Prepare the dividend
SDNode *Dividend;
if (is32Bit)
Dividend = CurDAG->getTargetNode(SystemZ::MOVSX64rr32, dl, MVT::i64, N0);
Dividend = CurDAG->getTargetNode(SystemZ::MOVSX64rr32, dl, EVT::i64, N0);
else
Dividend = N0.getNode();
@@ -679,7 +679,7 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
Dividend =
CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, ResVT,
SDValue(Tmp, 0), SDValue(Dividend, 0),
CurDAG->getTargetConstant(subreg_odd, MVT::i32));
CurDAG->getTargetConstant(subreg_odd, EVT::i32));
SDNode *Result;
SDValue DivVal = SDValue(Dividend, 0);
@@ -699,7 +699,7 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
dl, NVT,
SDValue(Result, 0),
CurDAG->getTargetConstant(SubRegIdx,
MVT::i32));
EVT::i32));
ReplaceUses(Op.getValue(0), SDValue(Div, 0));
#ifndef NDEBUG
@@ -716,7 +716,7 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
dl, NVT,
SDValue(Result, 0),
CurDAG->getTargetConstant(SubRegIdx,
MVT::i32));
EVT::i32));
ReplaceUses(Op.getValue(1), SDValue(Rem, 0));
#ifndef NDEBUG
@@ -736,21 +736,21 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
unsigned Opc, MOpc, ClrOpc;
SDValue N0 = Node->getOperand(0);
SDValue N1 = Node->getOperand(1);
MVT ResVT;
EVT ResVT;
bool is32Bit = false;
switch (NVT.getSimpleVT()) {
default: assert(0 && "Unsupported VT!");
case MVT::i32:
case EVT::i32:
Opc = SystemZ::UDIVREM32r; MOpc = SystemZ::UDIVREM32m;
ClrOpc = SystemZ::MOV64Pr0_even;
ResVT = MVT::v2i32;
ResVT = EVT::v2i32;
is32Bit = true;
break;
case MVT::i64:
case EVT::i64:
Opc = SystemZ::UDIVREM64r; MOpc = SystemZ::UDIVREM64m;
ClrOpc = SystemZ::MOV128r0_even;
ResVT = MVT::v2i64;
ResVT = EVT::v2i64;
break;
}
@@ -768,7 +768,7 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
Dividend =
CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, ResVT,
SDValue(Tmp, 0), SDValue(Dividend, 0),
CurDAG->getTargetConstant(SubRegIdx, MVT::i32));
CurDAG->getTargetConstant(SubRegIdx, EVT::i32));
}
// Zero out even subreg
@@ -793,7 +793,7 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
dl, NVT,
SDValue(Result, 0),
CurDAG->getTargetConstant(SubRegIdx,
MVT::i32));
EVT::i32));
ReplaceUses(Op.getValue(0), SDValue(Div, 0));
#ifndef NDEBUG
DOUT << std::string(Indent-2, ' ') << "=> ";
@@ -809,7 +809,7 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
dl, NVT,
SDValue(Result, 0),
CurDAG->getTargetConstant(SubRegIdx,
MVT::i32));
EVT::i32));
ReplaceUses(Op.getValue(1), SDValue(Rem, 0));
#ifndef NDEBUG
DOUT << std::string(Indent-2, ' ') << "=> ";