mirror of
https://github.com/c64scene-ar/llvm-6502.git
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Some improvements related to the computation of isReachable.
This fixes Bugzilla #1835 (http://llvm.org/bugs/show_bug.cgi?id=1835). This patched is reviewed by Tanya and Dan. Dan tested and approved it. The reason for the bad performance of the old algorithm is that it is very naive and scans every time all nodes of the DAG in the worst case. This patch introduces a new algorithm based on the paper "Online algorithms for maintaining the topological order of a directed acyclic graph" by David J.Pearce and Paul H.J.Kelly. This is the MNR algorithm. It has a linear time worst-case and performs much better in most situations. The paper can be found here: http://fano.ics.uci.edu/cites/Document/Online-algorithms-for-maintaining-the-topological-order-of-a-directed-acyclic-graph.html The main idea of the new algorithm is to compute the topological ordering of the SNodes in the DAG and to maintain it even after DAG modifications. The topological ordering allows for very fast node reachability checks. Tests on very big input files with tens of thousands of instructions in a BB indicate huge speed-ups (up to 10x compilation time improvement) compared to the old version. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48817 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Roman Levenstein
parent
7aae876db1
commit
e513ba4958
@ -81,6 +81,24 @@ public:
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void Schedule();
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/// IsReachable - Checks if SU is reachable from TargetSU
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bool IsReachable(SUnit *SU, SUnit *TargetSU);
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/// willCreateCycle - Returns true if adding an edge from SU to TargetSU will
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/// create a cycle.
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bool WillCreateCycle(SUnit *SU, SUnit *TargetSU);
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/// AddPred - This adds the specified node X as a predecessor of
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/// the current node Y if not already.
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/// This returns true if this is a new pred.
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/// Updates the topological oredering if required.
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bool AddPred(SUnit *Y, SUnit *X, bool isCtrl, bool isSpecial,
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unsigned PhyReg = 0, int Cost = 1);
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/// RemovePred - This removes the specified node N from predecessors of
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/// the current node M. Updates the topological oredering if required
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bool RemovePred(SUnit *M, SUnit *N, bool isCtrl, bool isSpecial);
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private:
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void ReleasePred(SUnit*, bool, unsigned);
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void ReleaseSucc(SUnit*, bool isChain, unsigned);
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@ -98,6 +116,84 @@ private:
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void ListScheduleTopDown();
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void ListScheduleBottomUp();
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void CommuteNodesToReducePressure();
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/// CreateNewSUnit - Creates a new SUnit and returns a pointer to it.
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/// Updates the topological oredering if required.
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SUnit *CreateNewSUnit(SDNode *N) {
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SUnit *NewNode = NewSUnit(N);
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// Update the topologic ordering
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if (NewNode->NodeNum >= Node2Index.size())
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InitDAGTopologicalSorting();
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return NewNode;
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}
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/// CreateClone - Creates a new SUnit from old one.
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/// Updates the topological oredering if required.
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SUnit *CreateClone(SUnit *N) {
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SUnit *NewNode = Clone(N);
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// Update the topologic ordering
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if (NewNode->NodeNum >= Node2Index.size())
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InitDAGTopologicalSorting();
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return NewNode;
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}
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/// Functions for preserving the topological ordering
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/// even after dynamic insertions of new edges.
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/// This allows for very fast implementation of IsReachable.
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/**
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The idea of the algorithm is taken from
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"Online algorithms for managing the topological order of
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a directed acyclic graph" by David J.Pearce and Paul H.J. Kelly
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This is the MNR algorithm, which is first introduced by
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A.Marchetti-Spaccamela, U.Nanni and H.Rohnert in
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"Maintaining a topological order under edge insertions".
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Short description of the algorithm:
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Topological ordering, ord, of a DAG maps each node to a topological
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index so that fall all edges X->Y it is the case that ord(X) < ord(Y).
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This means that if there is a path from the node X to the node Z,
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then ord(X) < ord(Z).
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This property can be used to check for reachability of nodes:
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if Z is reachable from X, then an insertion of the edge Z->X would
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create a cycle.
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Algorithm first computes a topological ordering for a DAG by initializing
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the Index2Node and Node2Index arrays and then tries to keep the ordering
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up-to-date after edge insertions by reordering the DAG.
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On insertion of the edge X->Y, the algorithm first marks by calling DFS the
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nodes reachable from Y, and then shifts them using Shift to lie immediately
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after X in Index2Node.
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*/
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/// InitDAGTopologicalSorting - create the initial topological
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/// ordering from the DAG to be scheduled
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void InitDAGTopologicalSorting();
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/// DFS - make a DFS traversal and mark all nodes affected by the
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/// edge insertion. These nodes should later get new topological indexes
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/// by means of Shift method
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void DFS(SUnit *SU, int UpperBound, bool& HasLoop);
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/// Shift - reassign topological indexes for the nodes in the DAG
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/// to preserve the topological ordering
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void Shift(BitVector& Visited, int LowerBound, int UpperBound);
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/// Allocate - assign the topological index to a node n
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void Allocate(int n, int index);
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/// Index2Node - Maps topological index to the node number
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std::vector<int> Index2Node;
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/// Node2Index - Maps the node number to its topological index
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std::vector<int> Node2Index;
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/// Visited - a set of nodes visited during a DFS traversal
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BitVector Visited;
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};
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} // end anonymous namespace
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@ -116,6 +212,7 @@ void ScheduleDAGRRList::Schedule() {
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SUnits[su].dumpAll(&DAG));
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CalculateDepths();
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CalculateHeights();
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InitDAGTopologicalSorting();
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AvailableQueue->initNodes(SUnitMap, SUnits);
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@ -326,36 +423,185 @@ void ScheduleDAGRRList::UnscheduleNodeBottomUp(SUnit *SU) {
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AvailableQueue->push(SU);
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}
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// FIXME: This is probably too slow!
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static void isReachable(SUnit *SU, SUnit *TargetSU,
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SmallPtrSet<SUnit*, 32> &Visited, bool &Reached) {
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if (Reached) return;
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if (SU == TargetSU) {
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Reached = true;
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return;
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/// IsReachable - Checks if SU is reachable from TargetSU.
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bool ScheduleDAGRRList::IsReachable(SUnit *SU, SUnit *TargetSU) {
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// If insertion of the edge SU->TargetSU would creates a cycle
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// then there is a path from TargetSU to SU
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int UpperBound, LowerBound;
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LowerBound = Node2Index[TargetSU->NodeNum];
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UpperBound = Node2Index[SU->NodeNum];
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bool HasLoop = false;
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// Is Ord(TargetSU) < Ord(SU) ?
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if (LowerBound < UpperBound) {
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Visited.reset();
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// There may be a path from TargetSU to SU. Check for it.
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DFS(TargetSU, UpperBound, HasLoop);
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}
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if (!Visited.insert(SU)) return;
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for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); I != E;
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++I)
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isReachable(I->Dep, TargetSU, Visited, Reached);
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return HasLoop;
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}
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static bool isReachable(SUnit *SU, SUnit *TargetSU) {
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SmallPtrSet<SUnit*, 32> Visited;
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bool Reached = false;
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isReachable(SU, TargetSU, Visited, Reached);
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return Reached;
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/// Allocate - assign the topological index to a node n
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inline void ScheduleDAGRRList::Allocate(int n, int index) {
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Node2Index[n] = index;
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Index2Node[index] = n;
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}
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/// InitDAGTopologicalSorting - create the initial topological
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/// ordering from the DAG to be scheduled.
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void ScheduleDAGRRList::InitDAGTopologicalSorting() {
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unsigned DAGSize = SUnits.size();
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std::vector<unsigned> InDegree(DAGSize);
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std::vector<SUnit*> WorkList;
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WorkList.reserve(DAGSize);
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std::vector<SUnit*> TopOrder;
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TopOrder.reserve(DAGSize);
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// Initialize the data structures
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for (unsigned i = 0, e = DAGSize; i != e; ++i) {
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SUnit *SU = &SUnits[i];
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int NodeNum = SU->NodeNum;
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unsigned Degree = SU->Succs.size();
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InDegree[NodeNum] = Degree;
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// Is it a node without dependencies?
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if (Degree == 0) {
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assert(SU->Succs.empty() && "SUnit should have no successors");
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// Collect leaf nodes
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WorkList.push_back(SU);
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}
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}
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while (!WorkList.empty()) {
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SUnit *SU = WorkList.back();
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WorkList.pop_back();
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TopOrder.push_back(SU);
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for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
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I != E; ++I) {
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SUnit *SU = I->Dep;
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if (!--InDegree[SU->NodeNum])
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// If all dependencies of the node are processed already,
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// then the node can be computed now
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WorkList.push_back(SU);
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}
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}
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// Second pass, assign the actual topological order as node ids.
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int Id = 0;
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Index2Node.clear();
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Node2Index.clear();
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Index2Node.resize(DAGSize);
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Node2Index.resize(DAGSize);
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Visited.resize(DAGSize);
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for (std::vector<SUnit*>::reverse_iterator TI = TopOrder.rbegin(),
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TE = TopOrder.rend();TI != TE; ++TI) {
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Allocate((*TI)->NodeNum, Id);
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Id++;
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}
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#ifndef NDEBUG
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// Check correctness of the ordering
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for (unsigned i = 0, e = DAGSize; i != e; ++i) {
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SUnit *SU = &SUnits[i];
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for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
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I != E; ++I) {
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assert(Node2Index[SU->NodeNum] > Node2Index[I->Dep->NodeNum] &&
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"Wrong topological sorting");
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}
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}
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#endif
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}
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/// AddPred - adds edge from SUnit X to SUnit Y
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/// Updates the topological oredering if required.
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bool ScheduleDAGRRList::AddPred(SUnit *Y, SUnit *X, bool isCtrl, bool isSpecial,
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unsigned PhyReg, int Cost) {
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int UpperBound, LowerBound;
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LowerBound = Node2Index[Y->NodeNum];
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UpperBound = Node2Index[X->NodeNum];
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bool HasLoop = false;
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// Is Ord(X) < Ord(Y) ?
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if (LowerBound < UpperBound) {
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// Update the topological order
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Visited.reset();
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DFS(Y, UpperBound, HasLoop);
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assert(!HasLoop && "Inserted edge creates a loop!");
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// Recompute topological indexes
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Shift(Visited, LowerBound, UpperBound);
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}
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// Now really insert the edge
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return Y->addPred(X,isCtrl,isSpecial,PhyReg,Cost);
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}
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/// RemovePred - This removes the specified node N from preds of
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/// the current node M. Updates the topological oredering if required
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bool ScheduleDAGRRList::RemovePred(SUnit *M, SUnit *N,
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bool isCtrl, bool isSpecial) {
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// InitDAGTopologicalSorting();
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return M->removePred(N, isCtrl, isSpecial);
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}
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/// DFS - make a DFS traversal to mark all nodes reachable from SU and and mark /// all nodes affected by the edge insertion. These nodes should later get new /// topological indexes by means of the Shift method
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void ScheduleDAGRRList::DFS(SUnit *SU, int UpperBound, bool& HasLoop) {
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std::vector<SUnit*> WorkList;
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WorkList.reserve(SUnits.size());
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WorkList.push_back(SU);
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while (!WorkList.empty()) {
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SU = WorkList.back();
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WorkList.pop_back();
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Visited.set(SU->NodeNum);
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for (int I = SU->Succs.size()-1; I >= 0; --I) {
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int s = SU->Succs[I].Dep->NodeNum;
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if (Node2Index[s] == UpperBound) {
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HasLoop = true;
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return;
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}
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// Visit successors if not already and is in affected region
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if (!Visited.test(s) && Node2Index[s] < UpperBound) {
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WorkList.push_back(SU->Succs[I].Dep);
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}
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}
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}
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}
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/// Shift - renumber the nodes so that the topological ordering is
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/// preserved
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void ScheduleDAGRRList::Shift(BitVector& Visited, int LowerBound,
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int UpperBound) {
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std::vector<int> L;
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int shift = 0;
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int i;
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for (i = LowerBound; i <= UpperBound; ++i) {
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// w is node at topological index i
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int w = Index2Node[i];
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if (Visited.test(w)) {
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// Unmark
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Visited.reset(w);
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L.push_back(w);
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shift = shift + 1;
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} else {
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Allocate(w, i - shift);
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}
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}
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for (unsigned j = 0; j < L.size(); ++j) {
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Allocate(L[j], i - shift);
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i = i + 1;
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}
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}
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/// WillCreateCycle - Returns true if adding an edge from SU to TargetSU will
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/// create a cycle.
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static bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) {
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if (isReachable(TargetSU, SU))
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bool ScheduleDAGRRList::WillCreateCycle(SUnit *SU, SUnit *TargetSU) {
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if (IsReachable(TargetSU, SU))
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return true;
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for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
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I != E; ++I)
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if (I->Cost < 0 && isReachable(TargetSU, I->Dep))
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if (I->Cost < 0 && IsReachable(TargetSU, I->Dep))
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return true;
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return false;
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}
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@ -428,7 +674,7 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
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DAG.ReplaceAllUsesOfValueWith(SDOperand(SU->Node, OldNumVals-1),
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SDOperand(LoadNode, 1));
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SUnit *NewSU = NewSUnit(N);
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SUnit *NewSU = CreateNewSUnit(N);
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SUnitMap[N].push_back(NewSU);
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const TargetInstrDesc &TID = TII->get(N->getTargetOpcode());
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for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
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@ -455,7 +701,7 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
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LoadSU = SMI->second.front();
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isNewLoad = false;
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} else {
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LoadSU = NewSUnit(LoadNode);
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LoadSU = CreateNewSUnit(LoadNode);
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SUnitMap[LoadNode].push_back(LoadSU);
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LoadSU->Depth = SU->Depth;
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@ -487,37 +733,41 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
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I->isCtrl, I->isSpecial));
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}
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SU->removePred(ChainPred, true, false);
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if (isNewLoad)
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LoadSU->addPred(ChainPred, true, false);
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RemovePred(SU, ChainPred, true, false);
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if (isNewLoad) {
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AddPred(LoadSU,ChainPred, true, false);
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}
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for (unsigned i = 0, e = LoadPreds.size(); i != e; ++i) {
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SDep *Pred = &LoadPreds[i];
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SU->removePred(Pred->Dep, Pred->isCtrl, Pred->isSpecial);
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if (isNewLoad)
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LoadSU->addPred(Pred->Dep, Pred->isCtrl, Pred->isSpecial,
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RemovePred(SU, Pred->Dep, Pred->isCtrl, Pred->isSpecial);
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if (isNewLoad) {
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AddPred(LoadSU, Pred->Dep, Pred->isCtrl, Pred->isSpecial,
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Pred->Reg, Pred->Cost);
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}
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}
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for (unsigned i = 0, e = NodePreds.size(); i != e; ++i) {
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SDep *Pred = &NodePreds[i];
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SU->removePred(Pred->Dep, Pred->isCtrl, Pred->isSpecial);
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NewSU->addPred(Pred->Dep, Pred->isCtrl, Pred->isSpecial,
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RemovePred(SU, Pred->Dep, Pred->isCtrl, Pred->isSpecial);
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AddPred(NewSU, Pred->Dep, Pred->isCtrl, Pred->isSpecial,
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Pred->Reg, Pred->Cost);
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}
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for (unsigned i = 0, e = NodeSuccs.size(); i != e; ++i) {
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SDep *Succ = &NodeSuccs[i];
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Succ->Dep->removePred(SU, Succ->isCtrl, Succ->isSpecial);
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Succ->Dep->addPred(NewSU, Succ->isCtrl, Succ->isSpecial,
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RemovePred(Succ->Dep, SU, Succ->isCtrl, Succ->isSpecial);
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AddPred(Succ->Dep, NewSU, Succ->isCtrl, Succ->isSpecial,
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Succ->Reg, Succ->Cost);
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}
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for (unsigned i = 0, e = ChainSuccs.size(); i != e; ++i) {
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SDep *Succ = &ChainSuccs[i];
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Succ->Dep->removePred(SU, Succ->isCtrl, Succ->isSpecial);
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if (isNewLoad)
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Succ->Dep->addPred(LoadSU, Succ->isCtrl, Succ->isSpecial,
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RemovePred(Succ->Dep, SU, Succ->isCtrl, Succ->isSpecial);
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if (isNewLoad) {
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AddPred(Succ->Dep, LoadSU, Succ->isCtrl, Succ->isSpecial,
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Succ->Reg, Succ->Cost);
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}
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}
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if (isNewLoad)
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NewSU->addPred(LoadSU, false, false);
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if (isNewLoad) {
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AddPred(NewSU, LoadSU, false, false);
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}
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if (isNewLoad)
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AvailableQueue->addNode(LoadSU);
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@ -533,13 +783,13 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
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}
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DOUT << "Duplicating SU # " << SU->NodeNum << "\n";
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NewSU = Clone(SU);
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NewSU = CreateClone(SU);
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// New SUnit has the exact same predecessors.
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for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
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I != E; ++I)
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if (!I->isSpecial) {
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NewSU->addPred(I->Dep, I->isCtrl, false, I->Reg, I->Cost);
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AddPred(NewSU, I->Dep, I->isCtrl, false, I->Reg, I->Cost);
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NewSU->Depth = std::max(NewSU->Depth, I->Dep->Depth+1);
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}
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@ -552,14 +802,14 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
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continue;
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if (I->Dep->isScheduled) {
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NewSU->Height = std::max(NewSU->Height, I->Dep->Height+1);
|
||||
I->Dep->addPred(NewSU, I->isCtrl, false, I->Reg, I->Cost);
|
||||
AddPred(I->Dep, NewSU, I->isCtrl, false, I->Reg, I->Cost);
|
||||
DelDeps.push_back(std::make_pair(I->Dep, I->isCtrl));
|
||||
}
|
||||
}
|
||||
for (unsigned i = 0, e = DelDeps.size(); i != e; ++i) {
|
||||
SUnit *Succ = DelDeps[i].first;
|
||||
bool isCtrl = DelDeps[i].second;
|
||||
Succ->removePred(SU, isCtrl, false);
|
||||
RemovePred(Succ, SU, isCtrl, false);
|
||||
}
|
||||
|
||||
AvailableQueue->updateNode(SU);
|
||||
@ -575,13 +825,13 @@ void ScheduleDAGRRList::InsertCCCopiesAndMoveSuccs(SUnit *SU, unsigned Reg,
|
||||
const TargetRegisterClass *DestRC,
|
||||
const TargetRegisterClass *SrcRC,
|
||||
SmallVector<SUnit*, 2> &Copies) {
|
||||
SUnit *CopyFromSU = NewSUnit(NULL);
|
||||
SUnit *CopyFromSU = CreateNewSUnit(NULL);
|
||||
CopyFromSU->CopySrcRC = SrcRC;
|
||||
CopyFromSU->CopyDstRC = DestRC;
|
||||
CopyFromSU->Depth = SU->Depth;
|
||||
CopyFromSU->Height = SU->Height;
|
||||
|
||||
SUnit *CopyToSU = NewSUnit(NULL);
|
||||
SUnit *CopyToSU = CreateNewSUnit(NULL);
|
||||
CopyToSU->CopySrcRC = DestRC;
|
||||
CopyToSU->CopyDstRC = SrcRC;
|
||||
|
||||
@ -594,18 +844,18 @@ void ScheduleDAGRRList::InsertCCCopiesAndMoveSuccs(SUnit *SU, unsigned Reg,
|
||||
continue;
|
||||
if (I->Dep->isScheduled) {
|
||||
CopyToSU->Height = std::max(CopyToSU->Height, I->Dep->Height+1);
|
||||
I->Dep->addPred(CopyToSU, I->isCtrl, false, I->Reg, I->Cost);
|
||||
AddPred(I->Dep, CopyToSU, I->isCtrl, false, I->Reg, I->Cost);
|
||||
DelDeps.push_back(std::make_pair(I->Dep, I->isCtrl));
|
||||
}
|
||||
}
|
||||
for (unsigned i = 0, e = DelDeps.size(); i != e; ++i) {
|
||||
SUnit *Succ = DelDeps[i].first;
|
||||
bool isCtrl = DelDeps[i].second;
|
||||
Succ->removePred(SU, isCtrl, false);
|
||||
RemovePred(Succ, SU, isCtrl, false);
|
||||
}
|
||||
|
||||
CopyFromSU->addPred(SU, false, false, Reg, -1);
|
||||
CopyToSU->addPred(CopyFromSU, false, false, Reg, 1);
|
||||
AddPred(CopyFromSU, SU, false, false, Reg, -1);
|
||||
AddPred(CopyToSU, CopyFromSU, false, false, Reg, 1);
|
||||
|
||||
AvailableQueue->updateNode(SU);
|
||||
AvailableQueue->addNode(CopyFromSU);
|
||||
@ -739,7 +989,7 @@ void ScheduleDAGRRList::ListScheduleBottomUp() {
|
||||
OldSU->isAvailable = false;
|
||||
AvailableQueue->remove(OldSU);
|
||||
}
|
||||
TrySU->addPred(OldSU, true, true);
|
||||
AddPred(TrySU, OldSU, true, true);
|
||||
// If one or more successors has been unscheduled, then the current
|
||||
// node is no longer avaialable. Schedule a successor that's now
|
||||
// available instead.
|
||||
@ -778,14 +1028,14 @@ void ScheduleDAGRRList::ListScheduleBottomUp() {
|
||||
InsertCCCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies);
|
||||
DOUT << "Adding an edge from SU # " << TrySU->NodeNum
|
||||
<< " to SU #" << Copies.front()->NodeNum << "\n";
|
||||
TrySU->addPred(Copies.front(), true, true);
|
||||
AddPred(TrySU, Copies.front(), true, true);
|
||||
NewDef = Copies.back();
|
||||
}
|
||||
|
||||
DOUT << "Adding an edge from SU # " << NewDef->NodeNum
|
||||
<< " to SU #" << TrySU->NodeNum << "\n";
|
||||
LiveRegDefs[Reg] = NewDef;
|
||||
NewDef->addPred(TrySU, true, true);
|
||||
AddPred(NewDef, TrySU, true, true);
|
||||
TrySU->isAvailable = false;
|
||||
CurSU = NewDef;
|
||||
}
|
||||
@ -1064,10 +1314,11 @@ namespace {
|
||||
|
||||
const TargetInstrInfo *TII;
|
||||
const TargetRegisterInfo *TRI;
|
||||
ScheduleDAGRRList *scheduleDAG;
|
||||
public:
|
||||
explicit BURegReductionPriorityQueue(const TargetInstrInfo *tii,
|
||||
const TargetRegisterInfo *tri)
|
||||
: TII(tii), TRI(tri) {}
|
||||
: TII(tii), TRI(tri), scheduleDAG(NULL) {}
|
||||
|
||||
void initNodes(DenseMap<SDNode*, std::vector<SUnit*> > &sumap,
|
||||
std::vector<SUnit> &sunits) {
|
||||
@ -1125,6 +1376,10 @@ namespace {
|
||||
return SethiUllmanNumbers[SU->NodeNum];
|
||||
}
|
||||
|
||||
void setScheduleDAG(ScheduleDAGRRList *scheduleDag) {
|
||||
scheduleDAG = scheduleDag;
|
||||
}
|
||||
|
||||
private:
|
||||
bool canClobber(const SUnit *SU, const SUnit *Op);
|
||||
void AddPseudoTwoAddrDeps();
|
||||
@ -1400,10 +1655,10 @@ void BURegReductionPriorityQueue<SF>::AddPseudoTwoAddrDeps() {
|
||||
if ((!canClobber(SuccSU, DUSU) ||
|
||||
(hasCopyToRegUse(SU) && !hasCopyToRegUse(SuccSU)) ||
|
||||
(!SU->isCommutable && SuccSU->isCommutable)) &&
|
||||
!isReachable(SuccSU, SU)) {
|
||||
!scheduleDAG->IsReachable(SuccSU, SU)) {
|
||||
DOUT << "Adding an edge from SU # " << SU->NodeNum
|
||||
<< " to SU #" << SuccSU->NodeNum << "\n";
|
||||
SU->addPred(SuccSU, true, true);
|
||||
scheduleDAG->AddPred(SU, SuccSU, true, true);
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1569,8 +1824,14 @@ llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAGISel *IS,
|
||||
MachineBasicBlock *BB) {
|
||||
const TargetInstrInfo *TII = DAG->getTarget().getInstrInfo();
|
||||
const TargetRegisterInfo *TRI = DAG->getTarget().getRegisterInfo();
|
||||
return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), true,
|
||||
new BURegReductionPriorityQueue<bu_ls_rr_sort>(TII, TRI));
|
||||
|
||||
BURegReductionPriorityQueue<bu_ls_rr_sort> *priorityQueue =
|
||||
new BURegReductionPriorityQueue<bu_ls_rr_sort>(TII, TRI);
|
||||
|
||||
ScheduleDAGRRList * scheduleDAG =
|
||||
new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), true, priorityQueue);
|
||||
priorityQueue->setScheduleDAG(scheduleDAG);
|
||||
return scheduleDAG;
|
||||
}
|
||||
|
||||
llvm::ScheduleDAG* llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user