diff --git a/include/llvm/CodeGen/MachineInstr.h b/include/llvm/CodeGen/MachineInstr.h index bd23b5ad22c..239f879727e 100644 --- a/include/llvm/CodeGen/MachineInstr.h +++ b/include/llvm/CodeGen/MachineInstr.h @@ -234,7 +234,7 @@ public: extra.regNum = Reg; } - void setImmedValue(int immVal) { + void setImmedValue(int64_t immVal) { assert(isImmediate() && "Wrong MachineOperand mutator"); contents.immedVal = immVal; } @@ -245,6 +245,22 @@ public: "Wrong MachineOperand accessor"); extra.offset = Offset; } + + /// ChangeToImmediate - Replace this operand with a new immediate operand of + /// the specified value. If an operand is known to be an immediate already, + /// the setImmedValue method should be used. + void ChangeToImmediate(int64_t ImmVal) { + opType = MO_Immediate; + contents.immedVal = ImmVal; + } + + /// ChangeToRegister - Replace this operand with a new register operand of + /// the specified value. If an operand is known to be an register already, + /// the setReg method should be used. + void ChangeToRegister(unsigned Reg) { + opType = MO_VirtualRegister; + extra.regNum = Reg; + } friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop); @@ -436,7 +452,6 @@ public: //===--------------------------------------------------------------------===// // Accessors used to modify instructions in place. // - // FIXME: Move this stuff to MachineOperand itself! /// setOpcode - Replace the opcode of the current instruction with a new one. /// @@ -448,14 +463,6 @@ public: void RemoveOperand(unsigned i) { operands.erase(operands.begin()+i); } - - // Access to set the operands when building the machine instruction - // - void SetMachineOperandConst(unsigned i, - MachineOperand::MachineOperandType operandType, - int intValue); - - void SetMachineOperandReg(unsigned i, int regNum); }; //===----------------------------------------------------------------------===// diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp index 8c28c97b0ac..17144f55822 100644 --- a/lib/CodeGen/LiveIntervalAnalysis.cpp +++ b/lib/CodeGen/LiveIntervalAnalysis.cpp @@ -187,7 +187,7 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) { MRegisterInfo::isVirtualRegister(mop.getReg())) { // replace register with representative register unsigned reg = rep(mop.getReg()); - mii->SetMachineOperandReg(i, reg); + mii->getOperand(i).setReg(reg); LiveInterval &RegInt = getInterval(reg); RegInt.weight += @@ -263,7 +263,7 @@ addIntervalsForSpills(const LiveInterval &li, VirtRegMap &vrm, int slot) { if (NewRegLiveIn && mop.isUse()) { // We already emitted a reload of this value, reuse it for // subsequent operands. - MI->SetMachineOperandReg(i, NewRegLiveIn); + MI->getOperand(i).setReg(NewRegLiveIn); DEBUG(std::cerr << "\t\t\t\treused reload into reg" << NewRegLiveIn << " for operand #" << i << '\n'); } else if (MachineInstr* fmi = mri_->foldMemoryOperand(MI, i, slot)) { @@ -300,7 +300,7 @@ addIntervalsForSpills(const LiveInterval &li, VirtRegMap &vrm, int slot) { // create a new register for this spill NewRegLiveIn = mf_->getSSARegMap()->createVirtualRegister(rc); - MI->SetMachineOperandReg(i, NewRegLiveIn); + MI->getOperand(i).setReg(NewRegLiveIn); vrm.grow(); vrm.assignVirt2StackSlot(NewRegLiveIn, slot); LiveInterval& nI = getOrCreateInterval(NewRegLiveIn); diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp index 90cec5a0a0f..b1fb52a13a5 100644 --- a/lib/CodeGen/MachineInstr.cpp +++ b/lib/CodeGen/MachineInstr.cpp @@ -107,25 +107,6 @@ bool MachineInstr::OperandsComplete() const { return false; } -void -MachineInstr::SetMachineOperandConst(unsigned i, - MachineOperand::MachineOperandType opTy, - int intValue) { - assert(i < getNumOperands()); - operands[i].opType = opTy; - operands[i].contents.immedVal = intValue; - operands[i].extra.regNum = -1; - operands[i].flags = 0; -} - -void MachineInstr::SetMachineOperandReg(unsigned i, int regNum) { - assert(i < getNumOperands()); - - operands[i].opType = MachineOperand::MO_VirtualRegister; - operands[i].contents.GV = NULL; - operands[i].extra.regNum = regNum; -} - void MachineInstr::dump() const { std::cerr << " " << *this; } diff --git a/lib/CodeGen/RegAllocLocal.cpp b/lib/CodeGen/RegAllocLocal.cpp index f84f7e82ef0..e3921e4ed38 100644 --- a/lib/CodeGen/RegAllocLocal.cpp +++ b/lib/CodeGen/RegAllocLocal.cpp @@ -443,7 +443,7 @@ MachineInstr *RA::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI, // and return. if (unsigned PR = getVirt2PhysRegMapSlot(VirtReg)) { MarkPhysRegRecentlyUsed(PR); // Already have this value available! - MI->SetMachineOperandReg(OpNum, PR); // Assign the input register + MI->getOperand(OpNum).setReg(PR); // Assign the input register return MI; } @@ -481,7 +481,7 @@ MachineInstr *RA::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI, ++NumLoads; // Update statistics PhysRegsEverUsed[PhysReg] = true; - MI->SetMachineOperandReg(OpNum, PhysReg); // Assign the input register + MI->getOperand(OpNum).setReg(PhysReg); // Assign the input register return MI; } @@ -599,7 +599,7 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) { DestPhysReg = getReg(MBB, MI, DestVirtReg); PhysRegsEverUsed[DestPhysReg] = true; markVirtRegModified(DestVirtReg); - MI->SetMachineOperandReg(i, DestPhysReg); // Assign the output register + MI->getOperand(i).setReg(DestPhysReg); // Assign the output register } } diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp index f6a9a112df6..4e6e1d2705e 100644 --- a/lib/CodeGen/RegAllocSimple.cpp +++ b/lib/CodeGen/RegAllocSimple.cpp @@ -211,7 +211,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) { Virt2PhysRegMap[virtualReg] = physReg; } } - MI->SetMachineOperandReg(i, physReg); + MI->getOperand(i).setReg(physReg); DEBUG(std::cerr << "virt: " << virtualReg << ", phys: " << op.getReg() << "\n"); } diff --git a/lib/CodeGen/TwoAddressInstructionPass.cpp b/lib/CodeGen/TwoAddressInstructionPass.cpp index 48581eebc18..4bd20479ff7 100644 --- a/lib/CodeGen/TwoAddressInstructionPass.cpp +++ b/lib/CodeGen/TwoAddressInstructionPass.cpp @@ -200,7 +200,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) { for (unsigned i = 1, e = mi->getNumOperands(); i != e; ++i) { if (mi->getOperand(i).isRegister() && mi->getOperand(i).getReg() == regB) - mi->SetMachineOperandReg(i, regA); + mi->getOperand(i).setReg(regA); } } diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp index 912359d1375..533a53b8e8e 100644 --- a/lib/CodeGen/VirtRegMap.cpp +++ b/lib/CodeGen/VirtRegMap.cpp @@ -182,7 +182,7 @@ bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { } } PhysRegsUsed[PhysReg] = true; - MI.SetMachineOperandReg(i, PhysReg); + MI.getOperand(i).setReg(PhysReg); } else { PhysRegsUsed[MO.getReg()] = true; } @@ -458,7 +458,7 @@ namespace { // Any stores to this stack slot are not dead anymore. MaybeDeadStores.erase(NewOp.StackSlot); - MI->SetMachineOperandReg(NewOp.Operand, NewPhysReg); + MI->getOperand(NewOp.Operand).setReg(NewPhysReg); Spills.addAvailable(NewOp.StackSlot, NewPhysReg); ++NumLoads; @@ -536,7 +536,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { // This virtual register was assigned a physreg! unsigned Phys = VRM.getPhys(VirtReg); PhysRegsUsed[Phys] = true; - MI.SetMachineOperandReg(i, Phys); + MI.getOperand(i).setReg(Phys); continue; } @@ -567,7 +567,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { << MRI->getName(PhysReg) << " for vreg" << VirtReg <<" instead of reloading into physreg " << MRI->getName(VRM.getPhys(VirtReg)) << "\n"); - MI.SetMachineOperandReg(i, PhysReg); + MI.getOperand(i).setReg(PhysReg); // The only technical detail we have is that we don't know that // PhysReg won't be clobbered by a reloaded stack slot that occurs @@ -618,7 +618,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { << MRI->getName(PhysReg) << " for vreg" << VirtReg << " instead of reloading into same physreg.\n"); - MI.SetMachineOperandReg(i, PhysReg); + MI.getOperand(i).setReg(PhysReg); ++NumReused; continue; } @@ -633,7 +633,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { Spills.ClobberPhysReg(DesignatedReg); Spills.addAvailable(StackSlot, DesignatedReg); - MI.SetMachineOperandReg(i, DesignatedReg); + MI.getOperand(i).setReg(DesignatedReg); DEBUG(std::cerr << '\t' << *prior(MII)); ++NumReused; continue; @@ -662,7 +662,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { MaybeDeadStores.erase(StackSlot); Spills.addAvailable(StackSlot, PhysReg); ++NumLoads; - MI.SetMachineOperandReg(i, PhysReg); + MI.getOperand(i).setReg(PhysReg); DEBUG(std::cerr << '\t' << *prior(MII)); } @@ -817,7 +817,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { PhysRegsUsed[PhysReg] = true; MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC); DEBUG(std::cerr << "Store:\t" << *next(MII)); - MI.SetMachineOperandReg(i, PhysReg); + MI.getOperand(i).setReg(PhysReg); // Check to see if this is a noop copy. If so, eliminate the // instruction before considering the dest reg to be changed. diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp index 95f60ed2e60..55a98aa69e0 100644 --- a/lib/Target/Alpha/AlphaRegisterInfo.cpp +++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp @@ -216,7 +216,7 @@ AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { int FrameIndex = MI.getOperand(i).getFrameIndex(); // Add the base register of R30 (SP) or R15 (FP). - MI.SetMachineOperandReg(i + 1, FP ? Alpha::R15 : Alpha::R30); + MI.getOperand(i + 1).ChangeToRegister(FP ? Alpha::R15 : Alpha::R30); // Now add the frame object offset to the offset from the virtual frame index. int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex); @@ -233,15 +233,14 @@ AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { //so in this case, we need to use a temporary register, and move the original //inst off the SP/FP //fix up the old: - MI.SetMachineOperandReg(i + 1, Alpha::R28); - MI.SetMachineOperandConst(i, MachineOperand::MO_Immediate, - getLower16(Offset)); + MI.getOperand(i + 1).ChangeToRegister(Alpha::R28); + MI.getOperand(i).ChangeToImmediate(getLower16(Offset)); //insert the new MachineInstr* nMI=BuildMI(Alpha::LDAH, 2, Alpha::R28) .addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30); MBB.insert(II, nMI); } else { - MI.SetMachineOperandConst(i, MachineOperand::MO_Immediate, Offset); + MI.getOperand(i).ChangeToImmediate(Offset); } } diff --git a/lib/Target/IA64/IA64RegisterInfo.cpp b/lib/Target/IA64/IA64RegisterInfo.cpp index 53fec20ec1f..931921254cc 100644 --- a/lib/Target/IA64/IA64RegisterInfo.cpp +++ b/lib/Target/IA64/IA64RegisterInfo.cpp @@ -155,7 +155,7 @@ void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const // choose a base register: ( hasFP? framepointer : stack pointer ) unsigned BaseRegister = FP ? IA64::r5 : IA64::r12; // Add the base register - MI.SetMachineOperandReg(i, BaseRegister); + MI.getOperand(i).ChangeToRegister(BaseRegister); // Now add the frame object offset to the offset from r1. int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex); @@ -168,7 +168,7 @@ void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const // XXX: we use 'r22' as another hack+slash temporary register here :( if ( Offset <= 8191 && Offset >= -8192) { // smallish offset //fix up the old: - MI.SetMachineOperandReg(i, IA64::r22); + MI.getOperand(i).ChangeToRegister(IA64::r22); MI.getOperand(i).setUse(); // mark r22 as being used // (the bundler wants to know this) //insert the new @@ -177,7 +177,7 @@ void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const MBB.insert(II, nMI); } else { // it's big //fix up the old: - MI.SetMachineOperandReg(i, IA64::r22); + MI.getOperand(i).ChangeToRegister(IA64::r22); MI.getOperand(i).setUse(); // mark r22 as being used // (the bundler wants to know this) MachineInstr* nMI; diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp index 037928fb315..d71f357990f 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -136,8 +136,8 @@ MachineInstr *PPCInstrInfo::commuteInstruction(MachineInstr *MI) const { // Swap op1/op2 unsigned Reg1 = MI->getOperand(1).getReg(); unsigned Reg2 = MI->getOperand(2).getReg(); - MI->SetMachineOperandReg(2, Reg1); - MI->SetMachineOperandReg(1, Reg2); + MI->getOperand(2).setReg(Reg1); + MI->getOperand(1).setReg(Reg2); // Swap the mask around. unsigned MB = MI->getOperand(4).getImmedValue(); diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index 24da5a378f6..36cb869abda 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -294,7 +294,7 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { int FrameIndex = MI.getOperand(i).getFrameIndex(); // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). - MI.SetMachineOperandReg(i, hasFP(MF) ? PPC::R31 : PPC::R1); + MI.getOperand(i).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1); // Take into account whether it's an add or mem instruction unsigned OffIdx = (i == 2) ? 1 : 2; @@ -321,8 +321,8 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { "No indexed form of load or store available!"); unsigned NewOpcode = ImmToIdxMap.find(MI.getOpcode())->second; MI.setOpcode(NewOpcode); - MI.SetMachineOperandReg(1, MI.getOperand(i).getReg()); - MI.SetMachineOperandReg(2, PPC::R0); + MI.getOperand(1).ChangeToRegister(MI.getOperand(i).getReg()); + MI.getOperand(2).ChangeToRegister(PPC::R0); } else { switch (MI.getOpcode()) { case PPC::LWA: @@ -333,7 +333,7 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { Offset >>= 2; // The actual encoded value has the low two bits zero. break; } - MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_Immediate, Offset); + MI.getOperand(OffIdx).ChangeToImmediate(Offset); } } diff --git a/lib/Target/Sparc/FPMover.cpp b/lib/Target/Sparc/FPMover.cpp index 70f203ccca9..7073260c4a9 100644 --- a/lib/Target/Sparc/FPMover.cpp +++ b/lib/Target/Sparc/FPMover.cpp @@ -104,8 +104,8 @@ bool FPMover::runOnMachineBasicBlock(MachineBasicBlock &MBB) { else assert(0 && "Unknown opcode!"); - MI->SetMachineOperandReg(0, EvenDestReg); - MI->SetMachineOperandReg(1, EvenSrcReg); + MI->getOperand(0).setReg(EvenDestReg); + MI->getOperand(1).setReg(EvenSrcReg); DEBUG(std::cerr << "FPMover: the modified instr is: " << *MI); // Insert copy for the other half of the double. if (DestDReg != SrcDReg) { diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp index d72ca74516b..88cbc9c769e 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.cpp +++ b/lib/Target/Sparc/SparcRegisterInfo.cpp @@ -135,8 +135,8 @@ SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { if (Offset >= -4096 && Offset <= 4095) { // If the offset is small enough to fit in the immediate field, directly // encode it. - MI.SetMachineOperandReg(i, SP::I6); - MI.SetMachineOperandConst(i+1, MachineOperand::MO_Immediate, Offset); + MI.getOperand(i).ChangeToRegister(SP::I6); + MI.getOperand(i+1).ChangeToImmediate(Offset); } else { // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to // scavenge a register here instead of reserving G1 all of the time. @@ -146,9 +146,8 @@ SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { BuildMI(*MI.getParent(), II, SP::ADDrr, 2, SP::G1).addReg(SP::G1).addReg(SP::I6); // Insert: G1+%lo(offset) into the user. - MI.SetMachineOperandReg(i, SP::G1); - MI.SetMachineOperandConst(i+1, MachineOperand::MO_Immediate, - Offset & ((1 << 10)-1)); + MI.getOperand(i).ChangeToRegister(SP::G1); + MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1)); } } diff --git a/lib/Target/TargetInstrInfo.cpp b/lib/Target/TargetInstrInfo.cpp index 60dd28c90a4..6377de88655 100644 --- a/lib/Target/TargetInstrInfo.cpp +++ b/lib/Target/TargetInstrInfo.cpp @@ -46,7 +46,7 @@ MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr *MI) const { "This only knows how to commute register operands so far"); unsigned Reg1 = MI->getOperand(1).getReg(); unsigned Reg2 = MI->getOperand(1).getReg(); - MI->SetMachineOperandReg(2, Reg1); - MI->SetMachineOperandReg(1, Reg2); + MI->getOperand(2).setReg(Reg1); + MI->getOperand(1).setReg(Reg2); return MI; } diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index 9f4a561d1a4..e34b5112a66 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -665,7 +665,7 @@ void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{ // This must be part of a four operand memory reference. Replace the // FrameIndex with base register with EBP. Add add an offset to the offset. - MI.SetMachineOperandReg(i, hasFP(MF) ? X86::EBP : X86::ESP); + MI.getOperand(i).ChangeToRegister(hasFP(MF) ? X86::EBP : X86::ESP); // Now add the frame object offset to the offset from EBP. int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + @@ -676,7 +676,7 @@ void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{ else Offset += 4; // Skip the saved EBP - MI.SetMachineOperandConst(i+3, MachineOperand::MO_Immediate, Offset); + MI.getOperand(i+3).ChangeToImmediate(Offset); } void