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https://github.com/c64scene-ar/llvm-6502.git
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[X86] Teach the DAGCombiner how to fold a OR of two shufflevector nodes.
This patch teaches the DAGCombiner how to fold a binary OR between two shufflevector into a single shuffle vector when possible. The rules are: 1. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask1) 2. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf B, A, Mask2) The DAGCombiner can take advantage of the fact that OR is commutative and compute two possible shuffle masks (Mask1 and Mask2) for the resulting shuffle node. Before folding a dag according to either rule 1 or 2, DAGCombiner verifies that the resulting shuffle mask is legal for the target. DAGCombiner would firstly try to fold according to 1.; If not possible then it will try to fold according to 2. If both Mask1 and Mask2 are illegal then we conservatively don't fold the OR instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203156 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrea Di Biagio
parent
d0d94d6afb
commit
e54158504f
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@ -3200,6 +3200,60 @@ SDValue DAGCombiner::visitOR(SDNode *N) {
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return N0;
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if (ISD::isBuildVectorAllOnes(N1.getNode()))
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return N1;
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// fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask1)
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// fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf B, A, Mask2)
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// Do this only if the resulting shuffle is legal.
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if (isa<ShuffleVectorSDNode>(N0) &&
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isa<ShuffleVectorSDNode>(N1) &&
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N0->getOperand(1) == N1->getOperand(1) &&
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ISD::isBuildVectorAllZeros(N0.getOperand(1).getNode())) {
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bool CanFold = true;
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unsigned NumElts = VT.getVectorNumElements();
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const ShuffleVectorSDNode *SV0 = cast<ShuffleVectorSDNode>(N0);
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const ShuffleVectorSDNode *SV1 = cast<ShuffleVectorSDNode>(N1);
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// We construct two shuffle masks:
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// - Mask1 is a shuffle mask for a shuffle with N0 as the first operand
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// and N1 as the second operand.
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// - Mask2 is a shuffle mask for a shuffle with N1 as the first operand
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// and N0 as the second operand.
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// We do this because OR is commutable and therefore there might be
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// two ways to fold this node into a shuffle.
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SmallVector<int,4> Mask1;
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SmallVector<int,4> Mask2;
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for (unsigned i = 0; i != NumElts && CanFold; ++i) {
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int M0 = SV0->getMaskElt(i);
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int M1 = SV1->getMaskElt(i);
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// Both shuffle indexes are undef. Propagate Undef.
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if (M0 < 0 && M1 < 0) {
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Mask1.push_back(M0);
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Mask2.push_back(M0);
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continue;
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}
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if (M0 < 0 || M1 < 0 ||
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(M0 < (int)NumElts && M1 < (int)NumElts) ||
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(M0 >= (int)NumElts && M1 >= (int)NumElts)) {
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CanFold = false;
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break;
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}
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Mask1.push_back(M0 < (int)NumElts ? M0 : M1 + NumElts);
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Mask2.push_back(M1 < (int)NumElts ? M1 : M0 + NumElts);
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}
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if (CanFold) {
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// Fold this sequence only if the resulting shuffle is 'legal'.
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if (TLI.isShuffleMaskLegal(Mask1, VT))
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return DAG.getVectorShuffle(VT, SDLoc(N), N0->getOperand(0),
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N1->getOperand(0), &Mask1[0]);
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if (TLI.isShuffleMaskLegal(Mask2, VT))
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return DAG.getVectorShuffle(VT, SDLoc(N), N1->getOperand(0),
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N0->getOperand(0), &Mask2[0]);
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}
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}
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}
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// fold (or x, undef) -> -1
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267
test/CodeGen/X86/combine-or.ll
Normal file
267
test/CodeGen/X86/combine-or.ll
Normal file
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@ -0,0 +1,267 @@
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 | FileCheck %s
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; Verify that each of the following test cases is folded into a single
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; instruction which performs a blend operation.
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define <2 x i64> @test1(<2 x i64> %a, <2 x i64> %b) {
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%shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32><i32 0, i32 2>
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%shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32><i32 2, i32 1>
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%or = or <2 x i64> %shuf1, %shuf2
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ret <2 x i64> %or
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}
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; CHECK-LABEL: test1
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; CHECK-NOT: xorps
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; CHECK: movsd
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; CHECK-NOT: orps
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; CHECK: ret
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define <4 x i32> @test2(<4 x i32> %a, <4 x i32> %b) {
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%shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 4, i32 2, i32 3>
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%shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 1, i32 4, i32 4>
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%or = or <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %or
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}
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; CHECK-LABEL: test2
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; CHECK-NOT: xorps
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; CHECK: shufps
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; CHECK: ret
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define <2 x i64> @test3(<2 x i64> %a, <2 x i64> %b) {
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%shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32><i32 2, i32 1>
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%shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32><i32 0, i32 2>
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%or = or <2 x i64> %shuf1, %shuf2
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ret <2 x i64> %or
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}
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; CHECK-LABEL: test3
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; CHECK-NOT: xorps
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; CHECK: movsd
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; CHECK-NEXT: ret
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define <4 x i32> @test4(<4 x i32> %a, <4 x i32> %b) {
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%shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 4, i32 4, i32 4>
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%shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 1, i32 2, i32 3>
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%or = or <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %or
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}
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; CHECK-LABEL: test4
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; CHECK-NOT: xorps
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; CHECK: movss
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; CHECK-NOT: orps
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; CHECK: ret
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define <4 x i32> @test5(<4 x i32> %a, <4 x i32> %b) {
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%shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 1, i32 2, i32 3>
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%shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 4, i32 4, i32 4>
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%or = or <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %or
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}
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; CHECK-LABEL: test5
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; CHECK-NOT: xorps
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; CHECK: movss
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; CHECK-NEXT: ret
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define <4 x i32> @test6(<4 x i32> %a, <4 x i32> %b) {
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%shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 1, i32 4, i32 4>
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%shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 4, i32 2, i32 3>
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%or = or <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %or
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}
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; CHECK-LABEL: test6
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; CHECK-NOT: xorps
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; CHECK: shufps
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; CHECK-NEXT: ret
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define <4 x i32> @test7(<4 x i32> %a, <4 x i32> %b) {
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%and1 = and <4 x i32> %a, <i32 -1, i32 -1, i32 0, i32 0>
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%and2 = and <4 x i32> %b, <i32 0, i32 0, i32 -1, i32 -1>
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%or = or <4 x i32> %and1, %and2
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ret <4 x i32> %or
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}
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; CHECK-LABEL: test7
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; CHECK-NOT: xorps
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; CHECK: shufps
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; CHECK-NEXT: ret
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define <2 x i64> @test8(<2 x i64> %a, <2 x i64> %b) {
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%and1 = and <2 x i64> %a, <i64 -1, i64 0>
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%and2 = and <2 x i64> %b, <i64 0, i64 -1>
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%or = or <2 x i64> %and1, %and2
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ret <2 x i64> %or
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}
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; CHECK-LABEL: test8
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; CHECK-NOT: xorps
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; CHECK: movsd
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; CHECK-NOT: orps
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; CHECK: ret
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define <4 x i32> @test9(<4 x i32> %a, <4 x i32> %b) {
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%and1 = and <4 x i32> %a, <i32 0, i32 0, i32 -1, i32 -1>
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%and2 = and <4 x i32> %b, <i32 -1, i32 -1, i32 0, i32 0>
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%or = or <4 x i32> %and1, %and2
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ret <4 x i32> %or
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}
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; CHECK-LABEL: test9
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; CHECK-NOT: xorps
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; CHECK: shufps
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; CHECK: ret
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define <2 x i64> @test10(<2 x i64> %a, <2 x i64> %b) {
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%and1 = and <2 x i64> %a, <i64 0, i64 -1>
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%and2 = and <2 x i64> %b, <i64 -1, i64 0>
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%or = or <2 x i64> %and1, %and2
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ret <2 x i64> %or
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}
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; CHECK-LABEL: test10
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; CHECK-NOT: xorps
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; CHECK: movsd
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; CHECK-NEXT: ret
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define <4 x i32> @test11(<4 x i32> %a, <4 x i32> %b) {
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%and1 = and <4 x i32> %a, <i32 -1, i32 0, i32 0, i32 0>
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%and2 = and <4 x i32> %b, <i32 0, i32 -1, i32 -1, i32 -1>
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%or = or <4 x i32> %and1, %and2
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ret <4 x i32> %or
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}
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; CHECK-LABEL: test11
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; CHECK-NOT: xorps
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; CHECK: movss
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; CHECK-NOT: orps
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; CHECK: ret
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define <4 x i32> @test12(<4 x i32> %a, <4 x i32> %b) {
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%and1 = and <4 x i32> %a, <i32 0, i32 -1, i32 -1, i32 -1>
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%and2 = and <4 x i32> %b, <i32 -1, i32 0, i32 0, i32 0>
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%or = or <4 x i32> %and1, %and2
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ret <4 x i32> %or
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}
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; CHECK-LABEL: test12
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; CHECK-NOT: xorps
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; CHECK: movss
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; CHECK-NEXT: ret
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; Verify that the following test cases are folded into single shuffles.
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define <4 x i32> @test13(<4 x i32> %a, <4 x i32> %b) {
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%shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 1, i32 1, i32 4, i32 4>
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%shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 4, i32 2, i32 3>
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%or = or <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %or
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}
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; CHECK-LABEL: test13
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; CHECK-NOT: xorps
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; CHECK: shufps
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; CHECK-NEXT: ret
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define <2 x i64> @test14(<2 x i64> %a, <2 x i64> %b) {
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%shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32><i32 0, i32 2>
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%shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32><i32 2, i32 0>
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%or = or <2 x i64> %shuf1, %shuf2
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ret <2 x i64> %or
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}
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; CHECK-LABEL: test14
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; CHECK-NOT: pslldq
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; CHECK-NOT: por
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; CHECK: punpcklqdq
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; CHECK-NEXT: ret
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define <4 x i32> @test15(<4 x i32> %a, <4 x i32> %b) {
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%shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 4, i32 2, i32 1>
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%shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 2, i32 1, i32 4, i32 4>
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%or = or <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %or
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}
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; CHECK-LABEL: test15
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; CHECK-NOT: xorps
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; CHECK: shufps
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; CHECK-NOT: shufps
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; CHECK-NOT: orps
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; CHECK: ret
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define <2 x i64> @test16(<2 x i64> %a, <2 x i64> %b) {
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%shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32><i32 2, i32 0>
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%shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32><i32 0, i32 2>
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%or = or <2 x i64> %shuf1, %shuf2
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ret <2 x i64> %or
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}
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; CHECK-LABEL: test16
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; CHECK-NOT: pslldq
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; CHECK-NOT: por
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; CHECK: punpcklqdq
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; CHECK: ret
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; Verify that the dag-combiner does not fold a OR of two shuffles into a single
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; shuffle instruction when the shuffle indexes are not compatible.
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define <4 x i32> @test17(<4 x i32> %a, <4 x i32> %b) {
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%shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 0, i32 4, i32 2>
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%shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 1, i32 4, i32 4>
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%or = or <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %or
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}
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; CHECK-LABEL: test17
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; CHECK: por
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; CHECK-NEXT: ret
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define <4 x i32> @test18(<4 x i32> %a, <4 x i32> %b) {
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%shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 0, i32 4, i32 4>
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%shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 4, i32 4, i32 4>
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%or = or <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %or
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}
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; CHECK-LABEL: test18
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; CHECK: orps
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; CHECK: ret
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define <4 x i32> @test19(<4 x i32> %a, <4 x i32> %b) {
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%shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 0, i32 4, i32 3>
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%shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 4, i32 2, i32 2>
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%or = or <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %or
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}
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; CHECK-LABEL: test19
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; CHECK: por
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; CHECK-NEXT: ret
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define <2 x i64> @test20(<2 x i64> %a, <2 x i64> %b) {
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%shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32><i32 0, i32 2>
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%shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32><i32 0, i32 2>
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%or = or <2 x i64> %shuf1, %shuf2
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ret <2 x i64> %or
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}
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; CHECK-LABEL: test20
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; CHECK-NOT: xorps
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; CHECK: orps
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; CHECK-NEXT: ret
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define <2 x i64> @test21(<2 x i64> %a, <2 x i64> %b) {
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%shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32><i32 2, i32 0>
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%shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32><i32 2, i32 0>
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%or = or <2 x i64> %shuf1, %shuf2
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ret <2 x i64> %or
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}
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; CHECK-LABEL: test21
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; CHECK: por
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; CHECK-NEXT: ret
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