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Fixed decoding for the ARM cdp2 instruction. The restriction on the coprocessor number was removed for this instruction.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155000 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Silviu Baranga 2012-04-18 13:02:55 +00:00
parent 9e71231309
commit e546c4c9c3
3 changed files with 10 additions and 1 deletions
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7
lib/Target/ARM/ARMInstrInfo.td
View File

@ -908,6 +908,11 @@ def p_imm : Operand<i32> {
let DecoderMethod = "DecodeCoprocessor";
}
def pf_imm : Operand<i32> {
let PrintMethod = "printPImmediate";
let ParserMatchClass = CoprocNumAsmOperand;
}
def CoprocRegAsmOperand : AsmOperandClass {
let Name = "CoprocReg";
let ParserMethod = "parseCoprocRegOperand";
@ -4306,7 +4311,7 @@ def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
let Inst{23-20} = opc1;
}
def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
def CDP2 : ABXI<0b1110, (outs), (ins pf_imm:$cop, imm0_15:$opc1,
c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
[(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,

3
test/MC/Disassembler/ARM/arm-tests.txt
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@ -321,3 +321,6 @@
# CHECK: ldmgt sp!, {r9}
0x00 0x02 0xbd 0xc8
# CHECK: cdp2 p10, #0, c6, c12, c0, #7
0xe0 0x6a 0x0c 0xfe

1
utils/TableGen/EDEmitter.cpp
View File

@ -594,6 +594,7 @@ static int ARMFlagFromOpName(LiteralConstantEmitter *type,
IMM("jtblock_operand");
IMM("nohash_imm");
IMM("p_imm");
IMM("pf_imm");
IMM("c_imm");
IMM("coproc_option_imm");
IMM("imod_op");