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https://github.com/c64scene-ar/llvm-6502.git
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[ARM64] Adds Cortex-A53 scheduling support for vector load/store post.
Patch by Dave Estes<cestes@codeaurora.org>! PR19761 http://reviews.llvm.org/D3829 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209176 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier
parent
f5d9170e67
commit
e55ae5f498
@ -841,10 +841,73 @@ bool ARM64InstrInfo::optimizeCompareInstr(
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}
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/// Return true if this is this instruction has a non-zero immediate
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bool ARM64InstrInfo::hasNonZeroImm(const MachineInstr *MI) const {
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if (MI->getOperand(3).isImm()) {
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unsigned val = MI->getOperand(3).getImm();
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return (val != 0);
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bool ARM64InstrInfo::hasShiftedReg(const MachineInstr *MI) const {
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switch (MI->getOpcode()) {
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default:
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break;
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case ARM64::ADDSWrs:
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case ARM64::ADDSXrs:
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case ARM64::ADDWrs:
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case ARM64::ADDXrs:
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case ARM64::ANDSWrs:
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case ARM64::ANDSXrs:
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case ARM64::ANDWrs:
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case ARM64::ANDXrs:
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case ARM64::BICSWrs:
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case ARM64::BICSXrs:
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case ARM64::BICWrs:
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case ARM64::BICXrs:
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case ARM64::CRC32Brr:
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case ARM64::CRC32CBrr:
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case ARM64::CRC32CHrr:
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case ARM64::CRC32CWrr:
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case ARM64::CRC32CXrr:
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case ARM64::CRC32Hrr:
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case ARM64::CRC32Wrr:
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case ARM64::CRC32Xrr:
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case ARM64::EONWrs:
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case ARM64::EONXrs:
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case ARM64::EORWrs:
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case ARM64::EORXrs:
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case ARM64::ORNWrs:
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case ARM64::ORNXrs:
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case ARM64::ORRWrs:
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case ARM64::ORRXrs:
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case ARM64::SUBSWrs:
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case ARM64::SUBSXrs:
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case ARM64::SUBWrs:
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case ARM64::SUBXrs:
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if (MI->getOperand(3).isImm()) {
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unsigned val = MI->getOperand(3).getImm();
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return (val != 0);
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}
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break;
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}
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return false;
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}
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/// Return true if this is this instruction has a non-zero immediate
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bool ARM64InstrInfo::hasExtendedReg(const MachineInstr *MI) const {
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switch (MI->getOpcode()) {
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default:
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break;
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case ARM64::ADDSWrx:
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case ARM64::ADDSXrx:
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case ARM64::ADDSXrx64:
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case ARM64::ADDWrx:
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case ARM64::ADDXrx:
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case ARM64::ADDXrx64:
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case ARM64::SUBSWrx:
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case ARM64::SUBSXrx:
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case ARM64::SUBSXrx64:
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case ARM64::SUBWrx:
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case ARM64::SUBXrx:
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case ARM64::SUBXrx64:
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if (MI->getOperand(3).isImm()) {
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unsigned val = MI->getOperand(3).getImm();
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return (val != 0);
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}
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break;
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}
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return false;
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@ -56,8 +56,13 @@ public:
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unsigned isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const override;
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/// \brief Is there a non-zero immediate?
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bool hasNonZeroImm(const MachineInstr *MI) const;
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/// Returns true if there is a shiftable register and that the shift value
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/// is non-zero.
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bool hasShiftedReg(const MachineInstr *MI) const;
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/// Returns true if there is an extendable register and that the extending value
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/// is non-zero.
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bool hasExtendedReg(const MachineInstr *MI) const;
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/// \brief Does this instruction set its full destination register to zero?
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bool isGPRZero(const MachineInstr *MI) const;
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@ -148,7 +148,9 @@ def : ReadAdvance<ReadVLD, 0>;
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// ALU - Most operands in the ALU pipes are not needed for two cycles. Shiftable
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// operands are needed one cycle later if and only if they are to be
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// shifted. Otherwise, they too are needed two cycle later.
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// shifted. Otherwise, they too are needed two cycle later. This same
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// ReadAdvance applies to Extended registers as well, even though there is
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// a seperate SchedPredicate for them.
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def : ReadAdvance<ReadI, 2, [WriteImm,WriteI,
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WriteISReg, WriteIEReg,WriteIS,
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WriteID32,WriteID64,
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@ -167,7 +169,7 @@ def A53ReadISReg : SchedReadVariant<[
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def : SchedAlias<ReadISReg, A53ReadISReg>;
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def A53ReadIEReg : SchedReadVariant<[
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SchedVar<RegShiftedPred, [A53ReadShifted]>,
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SchedVar<RegExtendedPred, [A53ReadShifted]>,
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SchedVar<NoSchedPred, [A53ReadNotShifted]>]>;
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def : SchedAlias<ReadIEReg, A53ReadIEReg>;
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@ -196,64 +198,83 @@ def : ReadAdvance<ReadID, 1, [WriteImm,WriteI,
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//---
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def : InstRW<[WriteI], (instrs COPY)>;
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//---
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// Vector Mul with Accumulate
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//---
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//def : InstRW<[WriteIM32, A53ReadIMA], (instregex "^M(ADD|SUB)W.*")>;
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//def : InstRW<[WriteIM64, A53ReadIMA], (instregex "^M(ADD|SUB)X.*")>;
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//---
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// Vector Loads
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//---
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def : InstRW<[A53WriteVLD1], (instregex "LD1i(8|16|32|64)(_POST)?$")>;
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def : InstRW<[A53WriteVLD1], (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)(_POST)?$")>;
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def : InstRW<[A53WriteVLD1], (instregex "LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)(_POST)?$")>;
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def : InstRW<[A53WriteVLD2], (instregex "LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)(_POST)?$")>;
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def : InstRW<[A53WriteVLD3], (instregex "LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)(_POST)?$")>;
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def : InstRW<[A53WriteVLD4], (instregex "LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)(_POST)?$")>;
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def : InstRW<[A53WriteVLD1], (instregex "LD1i(8|16|32|64)$")>;
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def : InstRW<[A53WriteVLD1], (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[A53WriteVLD1], (instregex "LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[A53WriteVLD2], (instregex "LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[A53WriteVLD3], (instregex "LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[A53WriteVLD4], (instregex "LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[A53WriteVLD1, WriteAdr], (instregex "LD1i(8|16|32|64)_POST$")>;
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def : InstRW<[A53WriteVLD1, WriteAdr], (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
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def : InstRW<[A53WriteVLD1, WriteAdr], (instregex "LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
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def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
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def : InstRW<[A53WriteVLD3, WriteAdr], (instregex "LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
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def : InstRW<[A53WriteVLD4, WriteAdr], (instregex "LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
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def : InstRW<[A53WriteVLD1], (instregex "LD2i(8|16|32|64)(_POST)?$")>;
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def : InstRW<[A53WriteVLD1], (instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)(_POST)?$")>;
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def : InstRW<[A53WriteVLD2], (instregex "LD2Twov(8b|4h|2s)(_POST)?$")>;
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def : InstRW<[A53WriteVLD4], (instregex "LD2Twov(16b|8h|4s|2d)(_POST)?$")>;
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def : InstRW<[A53WriteVLD1], (instregex "LD2i(8|16|32|64)$")>;
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def : InstRW<[A53WriteVLD1], (instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[A53WriteVLD2], (instregex "LD2Twov(8b|4h|2s)$")>;
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def : InstRW<[A53WriteVLD4], (instregex "LD2Twov(16b|8h|4s|2d)$")>;
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def : InstRW<[A53WriteVLD1, WriteAdr], (instregex "LD2i(8|16|32|64)(_POST)?$")>;
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def : InstRW<[A53WriteVLD1, WriteAdr], (instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)(_POST)?$")>;
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def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD2Twov(8b|4h|2s)(_POST)?$")>;
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def : InstRW<[A53WriteVLD4, WriteAdr], (instregex "LD2Twov(16b|8h|4s|2d)(_POST)?$")>;
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def : InstRW<[A53WriteVLD2], (instregex "LD3i(8|16|32|64)(_POST)?$")>;
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def : InstRW<[A53WriteVLD2], (instregex "LD3Rv(8b|4h|2s|1d|16b|8h|4s|2dq)(_POST)?$")>;
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def : InstRW<[A53WriteVLD4], (instregex "LD3Threev(8b|4h|2s|1d|16b|8h|4s)(_POST)?$")>;
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def : InstRW<[A53WriteVLD3], (instregex "LD3Threev(2d)(_POST)?$")>;
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def : InstRW<[A53WriteVLD2], (instregex "LD3i(8|16|32|64)$")>;
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def : InstRW<[A53WriteVLD2], (instregex "LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[A53WriteVLD4], (instregex "LD3Threev(8b|4h|2s|1d|16b|8h|4s)$")>;
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def : InstRW<[A53WriteVLD3], (instregex "LD3Threev(2d)$")>;
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def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD3i(8|16|32|64)_POST$")>;
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def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
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def : InstRW<[A53WriteVLD4, WriteAdr], (instregex "LD3Threev(8b|4h|2s|1d|16b|8h|4s)_POST$")>;
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def : InstRW<[A53WriteVLD3, WriteAdr], (instregex "LD3Threev(2d)_POST$")>;
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def : InstRW<[A53WriteVLD2], (instregex "LD4i(8|16|32|64)(_POST)?$")>;
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def : InstRW<[A53WriteVLD2], (instregex "LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)(_POST)?$")>;
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def : InstRW<[A53WriteVLD5], (instregex "LD4Fourv(8b|4h|2s|1d|16b|8h|4s)(_POST)?$")>;
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def : InstRW<[A53WriteVLD4], (instregex "LD4Fourv(2d)(_POST)?$")>;
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def : InstRW<[A53WriteVLD1, A53WriteVLD1], (instregex "LDN?PS.*$")>;
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def : InstRW<[A53WriteVLD2, A53WriteVLD2], (instregex "LDN?PD.*$")>;
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def : InstRW<[A53WriteVLD4, A53WriteVLD4], (instregex "LDN?PQ.*$")>;
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def : InstRW<[A53WriteVLD2], (instregex "LD4i(8|16|32|64)$")>;
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def : InstRW<[A53WriteVLD2], (instregex "LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[A53WriteVLD5], (instregex "LD4Fourv(8b|4h|2s|1d|16b|8h|4s)$")>;
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def : InstRW<[A53WriteVLD4], (instregex "LD4Fourv(2d)$")>;
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def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD4i(8|16|32|64)_POST$")>;
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def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
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def : InstRW<[A53WriteVLD5, WriteAdr], (instregex "LD4Fourv(8b|4h|2s|1d|16b|8h|4s)_POST$")>;
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def : InstRW<[A53WriteVLD4, WriteAdr], (instregex "LD4Fourv(2d)_POST$")>;
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//---
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// Vector Stores
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//---
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def : InstRW<[A53WriteVST1], (instregex "ST1i(8|16|32|64)(_POST)?$")>;
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def : InstRW<[A53WriteVST1], (instregex "ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)(_POST)?$")>;
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def : InstRW<[A53WriteVST1], (instregex "ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)(_POST)?$")>;
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def : InstRW<[A53WriteVST2], (instregex "ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)(_POST)?$")>;
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def : InstRW<[A53WriteVST2], (instregex "ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)(_POST)?$")>;
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def : InstRW<[A53WriteVST1], (instregex "ST1i(8|16|32|64)$")>;
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def : InstRW<[A53WriteVST1], (instregex "ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[A53WriteVST1], (instregex "ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[A53WriteVST2], (instregex "ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[A53WriteVST2], (instregex "ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[A53WriteVST1, WriteAdr], (instregex "ST1i(8|16|32|64)_POST$")>;
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def : InstRW<[A53WriteVST1, WriteAdr], (instregex "ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
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def : InstRW<[A53WriteVST1, WriteAdr], (instregex "ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
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def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
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def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
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def : InstRW<[A53WriteVST1], (instregex "ST2i(8|16|32|64)(_POST)?$")>;
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def : InstRW<[A53WriteVST1], (instregex "ST2Twov(8b|4h|2s)(_POST)?$")>;
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def : InstRW<[A53WriteVST2], (instregex "ST2Twov(16b|8h|4s|2d)(_POST)?$")>;
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def : InstRW<[A53WriteVST1], (instregex "ST2i(8|16|32|64)$")>;
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def : InstRW<[A53WriteVST1], (instregex "ST2Twov(8b|4h|2s)$")>;
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def : InstRW<[A53WriteVST2], (instregex "ST2Twov(16b|8h|4s|2d)$")>;
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def : InstRW<[A53WriteVST1, WriteAdr], (instregex "ST2i(8|16|32|64)_POST$")>;
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def : InstRW<[A53WriteVST1, WriteAdr], (instregex "ST2Twov(8b|4h|2s)_POST$")>;
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def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>;
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def : InstRW<[A53WriteVST2], (instregex "ST3i(8|16|32|64)(_POST)?$")>;
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def : InstRW<[A53WriteVST3], (instregex "ST3Threev(8b|4h|2s|1d|16b|8h|4s)(_POST)?$")>;
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def : InstRW<[A53WriteVST2], (instregex "ST3Threev(2d)(_POST)?$")>;
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def : InstRW<[A53WriteVST2], (instregex "ST3i(8|16|32|64)$")>;
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def : InstRW<[A53WriteVST3], (instregex "ST3Threev(8b|4h|2s|1d|16b|8h|4s)$")>;
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def : InstRW<[A53WriteVST2], (instregex "ST3Threev(2d)$")>;
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def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST3i(8|16|32|64)_POST$")>;
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def : InstRW<[A53WriteVST3, WriteAdr], (instregex "ST3Threev(8b|4h|2s|1d|16b|8h|4s)_POST$")>;
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def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST3Threev(2d)_POST$")>;
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def : InstRW<[A53WriteVST2], (instregex "ST4i(8|16|32|64)(_POST)?$")>;
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def : InstRW<[A53WriteVST3], (instregex "ST4Fourv(8b|4h|2s|1d|16b|8h|4s)(_POST)?$")>;
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def : InstRW<[A53WriteVST2], (instregex "ST4Fourv(2d)(_POST)?$")>;
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def : InstRW<[A53WriteVST1], (instregex "STN?P(S|D).*$")>;
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def : InstRW<[A53WriteVST2], (instregex "STN?PQ.*$")>;
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def : InstRW<[A53WriteVST2], (instregex "ST4i(8|16|32|64)$")>;
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def : InstRW<[A53WriteVST3], (instregex "ST4Fourv(8b|4h|2s|1d|16b|8h|4s)$")>;
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def : InstRW<[A53WriteVST2], (instregex "ST4Fourv(2d)$")>;
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def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST4i(8|16|32|64)_POST$")>;
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def : InstRW<[A53WriteVST3, WriteAdr], (instregex "ST4Fourv(8b|4h|2s|1d|16b|8h|4s)_POST$")>;
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def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST4Fourv(2d)_POST$")>;
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//---
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// Floating Point MAC, DIV, SQRT
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@ -51,7 +51,10 @@ def WriteSTIdx : SchedWrite; // Store to a register index (maybe scaled).
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def ReadAdrBase : SchedRead; // Read the base resister of a reg-offset LD/ST.
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// Predicate for determining when a shiftable register is shifted.
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def RegShiftedPred : SchedPredicate<[{TII->hasNonZeroImm(MI)}]>;
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def RegShiftedPred : SchedPredicate<[{TII->hasShiftedReg(MI)}]>;
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// Predicate for determining when a extendedable register is extended.
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def RegExtendedPred : SchedPredicate<[{TII->hasExtendedReg(MI)}]>;
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// ScaledIdxPred is true if a WriteLDIdx operand will be
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// scaled. Subtargets can use this to dynamically select resources and
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@ -108,3 +108,18 @@ declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i
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|
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attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
|
||||
attributes #1 = { nounwind }
|
||||
|
||||
|
||||
; Regression Test for Bug 19761
|
||||
; - [ARM64] Cortex-a53 schedule mode can't handle NEON post-increment load
|
||||
; - http://llvm.org/bugs/show_bug.cgi?id=19761
|
||||
;
|
||||
; Nothing explicit to check other than llc not crashing.
|
||||
define { <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld2(i8* %A, i8** %ptr) {
|
||||
%ld2 = tail call { <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld2.v16i8.p0i8(i8* %A)
|
||||
%tmp = getelementptr i8* %A, i32 32
|
||||
store i8* %tmp, i8** %ptr
|
||||
ret { <16 x i8>, <16 x i8> } %ld2
|
||||
}
|
||||
|
||||
declare { <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld2.v16i8.p0i8(i8*)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user