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R600/SI: Move selection of i64 add to separate function.
Also don't use a SmallVector for fixed size array. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211513 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -85,6 +85,8 @@ private:
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bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base, SDValue &Offset);
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bool SelectADDRIndirect(SDValue Addr, SDValue &Base, SDValue &Offset);
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SDNode *SelectADD_I64(SDNode *N);
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// Include the pieces autogenerated from the target description.
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#include "AMDGPUGenDAGISel.inc"
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};
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@ -217,45 +219,7 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
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ST.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS)
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break;
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SDLoc DL(N);
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SDValue LHS = N->getOperand(0);
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SDValue RHS = N->getOperand(1);
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SDValue Sub0 = CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32);
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SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32);
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SDNode *Lo0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
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DL, MVT::i32, LHS, Sub0);
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SDNode *Hi0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
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DL, MVT::i32, LHS, Sub1);
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SDNode *Lo1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
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DL, MVT::i32, RHS, Sub0);
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SDNode *Hi1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
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DL, MVT::i32, RHS, Sub1);
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SDVTList VTList = CurDAG->getVTList(MVT::i32, MVT::Glue);
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SmallVector<SDValue, 8> AddLoArgs;
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AddLoArgs.push_back(SDValue(Lo0, 0));
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AddLoArgs.push_back(SDValue(Lo1, 0));
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SDNode *AddLo = CurDAG->getMachineNode(
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isCFDepth0() ? AMDGPU::S_ADD_I32 : AMDGPU::V_ADD_I32_e32,
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DL, VTList, AddLoArgs);
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SDValue Carry = SDValue(AddLo, 1);
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SDNode *AddHi = CurDAG->getMachineNode(
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isCFDepth0() ? AMDGPU::S_ADDC_U32 : AMDGPU::V_ADDC_U32_e32,
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DL, MVT::i32, SDValue(Hi0, 0), SDValue(Hi1, 0), Carry);
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SDValue Args[5] = {
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CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, MVT::i32),
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SDValue(AddLo,0),
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Sub0,
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SDValue(AddHi,0),
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Sub1,
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};
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return CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, MVT::i64, Args);
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return SelectADD_I64(N);
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}
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case ISD::SCALAR_TO_VECTOR:
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case AMDGPUISD::BUILD_VERTICAL_VECTOR:
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@ -682,6 +646,46 @@ bool AMDGPUDAGToDAGISel::SelectADDRIndirect(SDValue Addr, SDValue &Base,
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return true;
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}
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SDNode *AMDGPUDAGToDAGISel::SelectADD_I64(SDNode *N) {
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SDLoc DL(N);
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SDValue LHS = N->getOperand(0);
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SDValue RHS = N->getOperand(1);
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SDValue Sub0 = CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32);
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SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32);
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SDNode *Lo0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
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DL, MVT::i32, LHS, Sub0);
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SDNode *Hi0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
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DL, MVT::i32, LHS, Sub1);
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SDNode *Lo1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
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DL, MVT::i32, RHS, Sub0);
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SDNode *Hi1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
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DL, MVT::i32, RHS, Sub1);
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SDVTList VTList = CurDAG->getVTList(MVT::i32, MVT::Glue);
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SDValue AddLoArgs[] = { SDValue(Lo0, 0), SDValue(Lo1, 0) };
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SDNode *AddLo = CurDAG->getMachineNode(
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isCFDepth0() ? AMDGPU::S_ADD_I32 : AMDGPU::V_ADD_I32_e32,
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DL, VTList, AddLoArgs);
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SDValue Carry = SDValue(AddLo, 1);
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SDNode *AddHi = CurDAG->getMachineNode(
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isCFDepth0() ? AMDGPU::S_ADDC_U32 : AMDGPU::V_ADDC_U32_e32,
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DL, MVT::i32, SDValue(Hi0, 0), SDValue(Hi1, 0), Carry);
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SDValue Args[5] = {
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CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, MVT::i32),
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SDValue(AddLo,0),
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Sub0,
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SDValue(AddHi,0),
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Sub1,
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};
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return CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, MVT::i64, Args);
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}
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void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
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const AMDGPUTargetLowering& Lowering =
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*static_cast<const AMDGPUTargetLowering*>(getTargetLowering());
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