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CreateVirtualRegisters does trivial copy coalescing. If a node def is used by a single CopyToReg, it reuses the virtual register assigned to the CopyToReg. This won't work for SDNode that is a clone or is itself cloned. Disable this optimization for those nodes or it can end up with non-SSA machine instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62356 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -250,6 +250,7 @@ namespace llvm {
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bool isAvailable : 1; // True once available.
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bool isScheduled : 1; // True once scheduled.
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bool isScheduleHigh : 1; // True if preferable to schedule high.
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bool isCloned : 1; // True if this node has been cloned.
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private:
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bool isDepthCurrent : 1; // True if Depth is current.
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bool isHeightCurrent : 1; // True if Height is current.
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@ -266,8 +267,8 @@ namespace llvm {
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Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0),
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isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false),
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isPending(false), isAvailable(false), isScheduled(false),
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isScheduleHigh(false), isDepthCurrent(false), isHeightCurrent(false),
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Depth(0), Height(0),
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isScheduleHigh(false), isCloned(false),
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isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
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CopyDstRC(NULL), CopySrcRC(NULL) {}
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/// SUnit - Construct an SUnit for post-regalloc scheduling to represent
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@ -277,8 +278,8 @@ namespace llvm {
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Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0),
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isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false),
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isPending(false), isAvailable(false), isScheduled(false),
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isScheduleHigh(false), isDepthCurrent(false), isHeightCurrent(false),
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Depth(0), Height(0),
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isScheduleHigh(false), isCloned(false),
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isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
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CopyDstRC(NULL), CopySrcRC(NULL) {}
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/// setNode - Assign the representative SDNode for this SUnit.
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@ -107,7 +107,7 @@ namespace llvm {
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/// VRBaseMap contains, for each already emitted node, the first virtual
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/// register number for the results of the node.
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///
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void EmitNode(SDNode *Node, bool IsClone,
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void EmitNode(SDNode *Node, bool IsClone, bool HasClone,
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DenseMap<SDValue, unsigned> &VRBaseMap);
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virtual MachineBasicBlock *EmitSchedule();
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@ -144,11 +144,12 @@ namespace llvm {
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/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
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/// implicit physical register output.
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void EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone,
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unsigned SrcReg,
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bool IsCloned, unsigned SrcReg,
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DenseMap<SDValue, unsigned> &VRBaseMap);
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void CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
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const TargetInstrDesc &II, bool IsClone,
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bool IsCloned,
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DenseMap<SDValue, unsigned> &VRBaseMap);
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/// BuildSchedUnits, AddSchedEdges - Helper functions for BuildSchedGraph.
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@ -33,6 +33,7 @@ SUnit *ScheduleDAGSDNodes::Clone(SUnit *Old) {
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SU->isTwoAddress = Old->isTwoAddress;
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SU->isCommutable = Old->isCommutable;
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SU->hasPhysRegDefs = Old->hasPhysRegDefs;
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Old->isCloned = true;
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return SU;
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}
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@ -46,7 +46,8 @@ getInstrOperandRegClass(const TargetRegisterInfo *TRI,
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/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
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/// implicit physical register output.
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void ScheduleDAGSDNodes::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
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bool IsClone, unsigned SrcReg,
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bool IsClone, bool IsCloned,
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unsigned SrcReg,
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DenseMap<SDValue, unsigned> &VRBaseMap) {
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unsigned VRBase = 0;
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if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
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@ -64,44 +65,45 @@ void ScheduleDAGSDNodes::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
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// the CopyToReg'd destination register instead of creating a new vreg.
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bool MatchReg = true;
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const TargetRegisterClass *UseRC = NULL;
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for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
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UI != E; ++UI) {
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SDNode *User = *UI;
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bool Match = true;
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if (User->getOpcode() == ISD::CopyToReg &&
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User->getOperand(2).getNode() == Node &&
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User->getOperand(2).getResNo() == ResNo) {
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unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
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if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
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VRBase = DestReg;
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Match = false;
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} else if (DestReg != SrcReg)
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Match = false;
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} else {
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for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
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SDValue Op = User->getOperand(i);
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if (Op.getNode() != Node || Op.getResNo() != ResNo)
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continue;
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MVT VT = Node->getValueType(Op.getResNo());
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if (VT == MVT::Other || VT == MVT::Flag)
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continue;
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Match = false;
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if (User->isMachineOpcode()) {
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const TargetInstrDesc &II = TII->get(User->getMachineOpcode());
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const TargetRegisterClass *RC =
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getInstrOperandRegClass(TRI,TII,II,i+II.getNumDefs());
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if (!UseRC)
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UseRC = RC;
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else if (RC)
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assert(UseRC == RC &&
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"Multiple uses expecting different register classes!");
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if (!IsClone && !IsCloned)
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for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
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UI != E; ++UI) {
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SDNode *User = *UI;
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bool Match = true;
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if (User->getOpcode() == ISD::CopyToReg &&
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User->getOperand(2).getNode() == Node &&
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User->getOperand(2).getResNo() == ResNo) {
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unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
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if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
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VRBase = DestReg;
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Match = false;
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} else if (DestReg != SrcReg)
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Match = false;
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} else {
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for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
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SDValue Op = User->getOperand(i);
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if (Op.getNode() != Node || Op.getResNo() != ResNo)
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continue;
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MVT VT = Node->getValueType(Op.getResNo());
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if (VT == MVT::Other || VT == MVT::Flag)
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continue;
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Match = false;
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if (User->isMachineOpcode()) {
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const TargetInstrDesc &II = TII->get(User->getMachineOpcode());
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const TargetRegisterClass *RC =
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getInstrOperandRegClass(TRI,TII,II,i+II.getNumDefs());
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if (!UseRC)
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UseRC = RC;
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else if (RC)
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assert(UseRC == RC &&
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"Multiple uses expecting different register classes!");
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}
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}
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}
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MatchReg &= Match;
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if (VRBase)
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break;
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}
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MatchReg &= Match;
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if (VRBase)
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break;
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}
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MVT VT = Node->getValueType(ResNo);
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const TargetRegisterClass *SrcRC = 0, *DstRC = 0;
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@ -157,7 +159,8 @@ unsigned ScheduleDAGSDNodes::getDstOfOnlyCopyToRegUse(SDNode *Node,
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}
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void ScheduleDAGSDNodes::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
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const TargetInstrDesc &II, bool IsClone,
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const TargetInstrDesc &II,
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bool IsClone, bool IsCloned,
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DenseMap<SDValue, unsigned> &VRBaseMap) {
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assert(Node->getMachineOpcode() != TargetInstrInfo::IMPLICIT_DEF &&
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"IMPLICIT_DEF should have been handled as a special case elsewhere!");
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@ -167,20 +170,22 @@ void ScheduleDAGSDNodes::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
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// is a vreg, use the CopyToReg'd destination register instead of creating
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// a new vreg.
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unsigned VRBase = 0;
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for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
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UI != E; ++UI) {
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SDNode *User = *UI;
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if (User->getOpcode() == ISD::CopyToReg &&
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User->getOperand(2).getNode() == Node &&
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User->getOperand(2).getResNo() == i) {
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unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
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if (TargetRegisterInfo::isVirtualRegister(Reg)) {
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VRBase = Reg;
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MI->addOperand(MachineOperand::CreateReg(Reg, true));
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break;
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if (!IsClone && !IsCloned)
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for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
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UI != E; ++UI) {
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SDNode *User = *UI;
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if (User->getOpcode() == ISD::CopyToReg &&
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User->getOperand(2).getNode() == Node &&
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User->getOperand(2).getResNo() == i) {
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unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
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if (TargetRegisterInfo::isVirtualRegister(Reg)) {
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VRBase = Reg;
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MI->addOperand(MachineOperand::CreateReg(Reg, true));
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break;
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}
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}
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}
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}
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// Create the result registers for this node and add the result regs to
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// the machine instruction.
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@ -452,7 +457,7 @@ void ScheduleDAGSDNodes::EmitSubregNode(SDNode *Node,
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/// EmitNode - Generate machine code for an node and needed dependencies.
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///
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void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone,
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void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
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DenseMap<SDValue, unsigned> &VRBaseMap) {
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// If machine instruction
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if (Node->isMachineOpcode()) {
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@ -489,7 +494,7 @@ void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone,
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// Add result register values for things that are defined by this
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// instruction.
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if (NumResults)
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CreateVirtualRegisters(Node, MI, II, IsClone, VRBaseMap);
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CreateVirtualRegisters(Node, MI, II, IsClone, IsCloned, VRBaseMap);
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// Emit all of the actual operands of this instruction, adding them to the
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// instruction as appropriate.
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@ -512,7 +517,7 @@ void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone,
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for (unsigned i = II.getNumDefs(); i < NumResults; ++i) {
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unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()];
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if (Node->hasAnyUseOfValue(i))
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EmitCopyFromReg(Node, i, IsClone, Reg, VRBaseMap);
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EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
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}
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}
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return;
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@ -559,7 +564,7 @@ void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone,
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}
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case ISD::CopyFromReg: {
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unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
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EmitCopyFromReg(Node, 0, IsClone, SrcReg, VRBaseMap);
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EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap);
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break;
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}
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case ISD::INLINEASM: {
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@ -636,13 +641,14 @@ MachineBasicBlock *ScheduleDAGSDNodes::EmitSchedule() {
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}
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SmallVector<SDNode *, 4> FlaggedNodes;
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for (SDNode *N = SU->getNode()->getFlaggedNode(); N; N = N->getFlaggedNode())
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for (SDNode *N = SU->getNode()->getFlaggedNode(); N;
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N = N->getFlaggedNode())
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FlaggedNodes.push_back(N);
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while (!FlaggedNodes.empty()) {
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EmitNode(FlaggedNodes.back(), SU->OrigNode != SU, VRBaseMap);
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EmitNode(FlaggedNodes.back(), SU->OrigNode != SU, SU->isCloned,VRBaseMap);
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FlaggedNodes.pop_back();
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}
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EmitNode(SU->getNode(), SU->OrigNode != SU, VRBaseMap);
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EmitNode(SU->getNode(), SU->OrigNode != SU, SU->isCloned, VRBaseMap);
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}
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return BB;
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50
test/CodeGen/X86/2009-01-16-SchedulerBug.ll
Normal file
50
test/CodeGen/X86/2009-01-16-SchedulerBug.ll
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@ -0,0 +1,50 @@
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; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin
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; rdar://6501631
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%CF = type { %Register }
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%XXV = type { i32 (...)** }
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%Register = type { %"struct.XXC::BCFs", i32 }
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%"struct.XXC::BCFs" = type { i32 }
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declare { i32, i1 } @llvm.sadd.with.overflow.i32(i32, i32) nounwind
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define fastcc %XXV* @bar(%CF* %call_frame, %XXV** %exception) nounwind {
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prologue:
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%param_x = load %XXV** null ; <%XXV*> [#uses=1]
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%unique_1.i = ptrtoint %XXV* %param_x to i1 ; <i1> [#uses=1]
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br i1 %unique_1.i, label %NextVerify42, label %FailedVerify
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NextVerify42: ; preds = %prologue
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%param_y = load %XXV** null ; <%XXV*> [#uses=1]
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%unique_1.i58 = ptrtoint %XXV* %param_y to i1 ; <i1> [#uses=1]
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br i1 %unique_1.i58, label %function_setup.cont, label %FailedVerify
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function_setup.cont: ; preds = %NextVerify42
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br i1 false, label %label13, label %label
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label: ; preds = %function_setup.cont
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%has_exn = icmp eq %XXV* null, null ; <i1> [#uses=1]
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br i1 %has_exn, label %kjsNumberLiteral.exit, label %handle_exception
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kjsNumberLiteral.exit: ; preds = %label
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%0 = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 0, i32 0) ; <{ i32, i1 }> [#uses=2]
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%intAdd = extractvalue { i32, i1 } %0, 0 ; <i32> [#uses=2]
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%intAddOverflow = extractvalue { i32, i1 } %0, 1 ; <i1> [#uses=1]
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%toint56 = ashr i32 %intAdd, 1 ; <i32> [#uses=1]
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%toFP57 = sitofp i32 %toint56 to double ; <double> [#uses=1]
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br i1 %intAddOverflow, label %rematerializeAdd, label %label13
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label13: ; preds = %kjsNumberLiteral.exit, %function_setup.cont
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%var_lr1.0 = phi double [ %toFP57, %kjsNumberLiteral.exit ], [ 0.000000e+00, %function_setup.cont ] ; <double> [#uses=0]
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unreachable
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FailedVerify: ; preds = %NextVerify42, %prologue
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ret %XXV* null
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rematerializeAdd: ; preds = %kjsNumberLiteral.exit
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%rematerializedInt = sub i32 %intAdd, 0 ; <i32> [#uses=0]
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ret %XXV* null
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handle_exception: ; preds = %label
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ret %XXV* undef
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}
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