mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-21 18:29:46 +00:00
Make x86's BT instruction matching more thorough, and add some
dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63266 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman
parent
63e3e6350b
commit
e5af2d3a22
@ -780,6 +780,8 @@ public:
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SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To);
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SDValue CombineTo(SDNode *N, SDValue Res);
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SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1);
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void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
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};
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/// SimplifySetCC - Try to simplify a setcc built with the specified operands
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@ -102,6 +102,8 @@ namespace {
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SDValue To[] = { Res0, Res1 };
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return CombineTo(N, To, 2, AddTo);
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}
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void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
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private:
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@ -298,6 +300,10 @@ CombineTo(SDNode *N, SDValue Res0, SDValue Res1) {
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return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1);
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}
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void TargetLowering::DAGCombinerInfo::
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CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
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return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
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}
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//===----------------------------------------------------------------------===//
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// Helper Functions
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@ -539,29 +545,14 @@ SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
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return SDValue(N, 0);
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}
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/// SimplifyDemandedBits - Check the specified integer node value to see if
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/// it can be simplified or if things it uses can be simplified by bit
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/// propagation. If so, return true.
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bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
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TargetLowering::TargetLoweringOpt TLO(DAG);
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APInt KnownZero, KnownOne;
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if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
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return false;
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// Revisit the node.
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AddToWorkList(Op.getNode());
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// Replace the old value with the new one.
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++NodesCombined;
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DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.getNode()->dump(&DAG));
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DOUT << "\nWith: "; DEBUG(TLO.New.getNode()->dump(&DAG));
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DOUT << '\n';
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void
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DAGCombiner::CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &
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TLO) {
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// Replace all uses. If any nodes become isomorphic to other nodes and
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// are deleted, make sure to remove them from our worklist.
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WorkListRemover DeadNodes(*this);
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DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
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// Push the new node and any (possibly new) users onto the worklist.
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AddToWorkList(TLO.New.getNode());
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AddUsersToWorkList(TLO.New.getNode());
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@ -580,6 +571,27 @@ bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
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DAG.DeleteNode(TLO.Old.getNode());
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}
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}
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/// SimplifyDemandedBits - Check the specified integer node value to see if
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/// it can be simplified or if things it uses can be simplified by bit
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/// propagation. If so, return true.
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bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
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TargetLowering::TargetLoweringOpt TLO(DAG);
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APInt KnownZero, KnownOne;
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if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
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return false;
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// Revisit the node.
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AddToWorkList(Op.getNode());
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// Replace the old value with the new one.
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++NodesCombined;
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DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.getNode()->dump(&DAG));
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DOUT << "\nWith: "; DEBUG(TLO.New.getNode()->dump(&DAG));
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DOUT << '\n';
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CommitTargetLoweringOpt(TLO);
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return true;
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}
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@ -724,7 +724,7 @@ TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
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bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
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const APInt &Demanded) {
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// FIXME: ISD::SELECT, ISD::SELECT_CC
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switch(Op.getOpcode()) {
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switch (Op.getOpcode()) {
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default: break;
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case ISD::AND:
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case ISD::OR:
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@ -1054,6 +1054,14 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
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}
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break;
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case ISD::SRA:
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// If this is an arithmetic shift right and only the low-bit is set, we can
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// always convert this into a logical shr, even if the shift amount is
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// variable. The low bit of the shift cannot be an input sign bit unless
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// the shift amount is >= the size of the datatype, which is undefined.
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if (DemandedMask == 1)
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return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, Op.getValueType(),
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Op.getOperand(0), Op.getOperand(1)));
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if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
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MVT VT = Op.getValueType();
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unsigned ShAmt = SA->getZExtValue();
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@ -1332,6 +1340,21 @@ unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
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return 1;
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}
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static bool ValueHasAtMostOneBitSet(SDValue Val, const SelectionDAG &DAG) {
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// Logical shift right or left won't ever introduce new set bits.
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// We check for this case because we don't care which bits are
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// set, but ComputeMaskedBits won't know anything unless it can
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// determine which specific bits may be set.
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if (Val.getOpcode() == ISD::SHL || Val.getOpcode() == ISD::SRL)
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return ValueHasAtMostOneBitSet(Val.getOperand(0), DAG);
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MVT OpVT = Val.getValueType();
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unsigned BitWidth = OpVT.getSizeInBits();
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APInt Mask = APInt::getAllOnesValue(BitWidth);
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APInt KnownZero, KnownOne;
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DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne);
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return KnownZero.countPopulation() == BitWidth - 1;
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}
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/// SimplifySetCC - Try to simplify a setcc built with the specified operands
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/// and cc. If it is unable to simplify it, return a null SDValue.
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@ -1791,6 +1814,24 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
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}
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}
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}
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// Simpify x&y == y to x&y == 0 if y has exactly one bit set.
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if (N0.getOpcode() == ISD::AND)
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if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
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if (ValueHasAtMostOneBitSet(N1, DAG)) {
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Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
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SDValue Zero = DAG.getConstant(0, N1.getValueType());
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return DAG.getSetCC(VT, N0, Zero, Cond);
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}
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}
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if (N1.getOpcode() == ISD::AND)
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if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
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if (ValueHasAtMostOneBitSet(N0, DAG)) {
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Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
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SDValue Zero = DAG.getConstant(0, N0.getValueType());
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return DAG.getSetCC(VT, N1, Zero, Cond);
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}
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}
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}
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// Fold away ALL boolean setcc's.
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@ -5114,22 +5114,39 @@ SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
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SDValue Op1 = Op.getOperand(1);
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ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
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// Lower (X & (1 << N)) == 0 to BT.
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// Lower ((X >>u N) & 1) != 0 to BT.
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// Lower ((X >>s N) & 1) != 0 to BT.
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// Lower (X & (1 << N)) == 0 to BT(X, N).
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// Lower ((X >>u N) & 1) != 0 to BT(X, N).
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// Lower ((X >>s N) & 1) != 0 to BT(X, N).
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if (Op0.getOpcode() == ISD::AND &&
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Op0.hasOneUse() &&
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Op1.getOpcode() == ISD::Constant &&
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Op0.getOperand(1).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(Op1)->getZExtValue() == 0 &&
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(CC == ISD::SETEQ || CC == ISD::SETNE)) {
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ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op0.getOperand(1));
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ConstantSDNode *CmpRHS = cast<ConstantSDNode>(Op1);
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SDValue AndLHS = Op0.getOperand(0);
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if (CmpRHS->getZExtValue() == 0 && AndRHS->getZExtValue() == 1 &&
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AndLHS.getOpcode() == ISD::SRL) {
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SDValue LHS = AndLHS.getOperand(0);
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SDValue RHS = AndLHS.getOperand(1);
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SDValue LHS, RHS;
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if (Op0.getOperand(1).getOpcode() == ISD::SHL) {
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if (ConstantSDNode *Op010C =
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dyn_cast<ConstantSDNode>(Op0.getOperand(1).getOperand(0)))
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if (Op010C->getZExtValue() == 1) {
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LHS = Op0.getOperand(0);
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RHS = Op0.getOperand(1).getOperand(1);
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}
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} else if (Op0.getOperand(0).getOpcode() == ISD::SHL) {
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if (ConstantSDNode *Op000C =
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dyn_cast<ConstantSDNode>(Op0.getOperand(0).getOperand(0)))
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if (Op000C->getZExtValue() == 1) {
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LHS = Op0.getOperand(1);
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RHS = Op0.getOperand(0).getOperand(1);
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}
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} else if (Op0.getOperand(1).getOpcode() == ISD::Constant) {
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ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op0.getOperand(1));
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SDValue AndLHS = Op0.getOperand(0);
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if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
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LHS = AndLHS.getOperand(0);
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RHS = AndLHS.getOperand(1);
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}
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}
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if (LHS.getNode()) {
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// If LHS is i8, promote it to i16 with any_extend. There is no i8 BT
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// instruction. Since the shift amount is in-range-or-undefined, we know
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// that doing a bittest on the i16 value is ok. We extend to i32 because
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@ -5141,10 +5158,10 @@ SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
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// BT ignores high bits (like shifts) we can use anyextend.
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if (LHS.getValueType() != RHS.getValueType())
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RHS = DAG.getNode(ISD::ANY_EXTEND, LHS.getValueType(), RHS);
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SDValue BT = DAG.getNode(X86ISD::BT, MVT::i32, LHS, RHS);
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unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
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return DAG.getNode(X86ISD::SETCC, MVT::i8,
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return DAG.getNode(X86ISD::SETCC, MVT::i8,
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DAG.getConstant(Cond, MVT::i8), BT);
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}
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}
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@ -5295,7 +5312,7 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
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!isScalarFPTypeInSSEReg(VT)) // FPStack?
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IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
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if (isX86LogicalCmp(Opc) && !IllegalFPCMov) {
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if ((isX86LogicalCmp(Opc) && !IllegalFPCMov) || Opc == X86ISD::BT) { // FIXME
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Cond = Cmp;
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addTest = false;
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}
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@ -7547,6 +7564,7 @@ static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
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/// PerformBuildVectorCombine - build_vector 0,(load i64 / f64) -> movq / movsd.
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static SDValue PerformBuildVectorCombine(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const X86Subtarget *Subtarget,
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const TargetLowering &TLI) {
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unsigned NumOps = N->getNumOperands();
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@ -7587,7 +7605,9 @@ static SDValue PerformBuildVectorCombine(SDNode *N, SelectionDAG &DAG,
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SDVTList Tys = DAG.getVTList(VT, MVT::Other);
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SDValue Ops[] = { LD->getChain(), LD->getBasePtr() };
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SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, Tys, Ops, 2);
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DAG.ReplaceAllUsesOfValueWith(SDValue(Base, 1), ResNode.getValue(1));
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TargetLowering::TargetLoweringOpt TLO(DAG);
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TLO.CombineTo(SDValue(Base, 1), ResNode.getValue(1));
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DCI.CommitTargetLoweringOpt(TLO);
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return ResNode;
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}
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@ -7875,6 +7895,23 @@ static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
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return SDValue();
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}
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static SDValue PerformBTCombine(SDNode *N,
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SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI) {
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// BT ignores high bits in the bit index operand.
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SDValue Op1 = N->getOperand(1);
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if (Op1.hasOneUse()) {
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unsigned BitWidth = Op1.getValueSizeInBits();
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APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
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APInt KnownZero, KnownOne;
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TargetLowering::TargetLoweringOpt TLO(DAG);
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TargetLowering &TLI = DAG.getTargetLoweringInfo();
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if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
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TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
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DCI.CommitTargetLoweringOpt(TLO);
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}
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return SDValue();
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}
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SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
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DAGCombinerInfo &DCI) const {
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@ -7883,7 +7920,7 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
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default: break;
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case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
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case ISD::BUILD_VECTOR:
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return PerformBuildVectorCombine(N, DAG, Subtarget, *this);
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return PerformBuildVectorCombine(N, DAG, DCI, Subtarget, *this);
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case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
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case ISD::SHL:
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case ISD::SRA:
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@ -7892,6 +7929,7 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
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case X86ISD::FXOR:
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case X86ISD::FOR: return PerformFORCombine(N, DAG);
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case X86ISD::FAND: return PerformFANDCombine(N, DAG);
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case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
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}
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return SDValue();
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@ -1,4 +1,4 @@
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; RUN: llvm-as < %s | llc | grep btl
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; RUN: llvm-as < %s | llc -march=x86 | grep btl | count 28
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; RUN: llvm-as < %s | llc -mcpu=pentium4 | grep btl | not grep esp
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; RUN: llvm-as < %s | llc -mcpu=penryn | grep btl | not grep esp
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; PR3253
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@ -7,8 +7,17 @@
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; pentium4, however it is currently disabled due to the register+memory
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; form having different semantics than the register+register form.
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
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target triple = "i386-apple-darwin8"
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; Test these patterns:
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; (X & (1 << N)) != 0 --> BT(X, N).
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; ((X >>u N) & 1) != 0 --> BT(X, N).
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; as well as several variations:
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; - The second form can use an arithmetic shift.
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; - Either form can use == instead of !=.
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; - Either form can compare with an operand of the &
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; instead of with 0.
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; - The comparison can be commuted (only cases where neither
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; operand is constant are included).
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; - The and can be commuted.
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define void @test2(i32 %x, i32 %n) nounwind {
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entry:
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@ -25,4 +34,409 @@ UnifiedReturnBlock: ; preds = %entry
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ret void
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}
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define void @test2b(i32 %x, i32 %n) nounwind {
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entry:
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%tmp29 = lshr i32 %x, %n ; <i32> [#uses=1]
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%tmp3 = and i32 1, %tmp29
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%tmp4 = icmp eq i32 %tmp3, 0 ; <i1> [#uses=1]
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br i1 %tmp4, label %bb, label %UnifiedReturnBlock
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bb: ; preds = %entry
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call void @foo()
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ret void
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UnifiedReturnBlock: ; preds = %entry
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ret void
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}
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define void @atest2(i32 %x, i32 %n) nounwind {
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entry:
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%tmp29 = ashr i32 %x, %n ; <i32> [#uses=1]
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%tmp3 = and i32 %tmp29, 1 ; <i32> [#uses=1]
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%tmp4 = icmp eq i32 %tmp3, 0 ; <i1> [#uses=1]
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br i1 %tmp4, label %bb, label %UnifiedReturnBlock
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bb: ; preds = %entry
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call void @foo()
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ret void
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UnifiedReturnBlock: ; preds = %entry
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ret void
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}
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define void @atest2b(i32 %x, i32 %n) nounwind {
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entry:
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%tmp29 = ashr i32 %x, %n ; <i32> [#uses=1]
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%tmp3 = and i32 1, %tmp29
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%tmp4 = icmp eq i32 %tmp3, 0 ; <i1> [#uses=1]
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br i1 %tmp4, label %bb, label %UnifiedReturnBlock
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bb: ; preds = %entry
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call void @foo()
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ret void
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UnifiedReturnBlock: ; preds = %entry
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ret void
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}
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define void @test3(i32 %x, i32 %n) nounwind {
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entry:
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%tmp29 = shl i32 1, %n ; <i32> [#uses=1]
|
||||
%tmp3 = and i32 %tmp29, %x ; <i32> [#uses=1]
|
||||
%tmp4 = icmp eq i32 %tmp3, 0 ; <i1> [#uses=1]
|
||||
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
|
||||
|
||||
bb: ; preds = %entry
|
||||
call void @foo()
|
||||
ret void
|
||||
|
||||
UnifiedReturnBlock: ; preds = %entry
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test3b(i32 %x, i32 %n) nounwind {
|
||||
entry:
|
||||
%tmp29 = shl i32 1, %n ; <i32> [#uses=1]
|
||||
%tmp3 = and i32 %x, %tmp29
|
||||
%tmp4 = icmp eq i32 %tmp3, 0 ; <i1> [#uses=1]
|
||||
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
|
||||
|
||||
bb: ; preds = %entry
|
||||
call void @foo()
|
||||
ret void
|
||||
|
||||
UnifiedReturnBlock: ; preds = %entry
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @testne2(i32 %x, i32 %n) nounwind {
|
||||
entry:
|
||||
%tmp29 = lshr i32 %x, %n ; <i32> [#uses=1]
|
||||
%tmp3 = and i32 %tmp29, 1 ; <i32> [#uses=1]
|
||||
%tmp4 = icmp ne i32 %tmp3, 0 ; <i1> [#uses=1]
|
||||
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
|
||||
|
||||
bb: ; preds = %entry
|
||||
call void @foo()
|
||||
ret void
|
||||
|
||||
UnifiedReturnBlock: ; preds = %entry
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @testne2b(i32 %x, i32 %n) nounwind {
|
||||
entry:
|
||||
%tmp29 = lshr i32 %x, %n ; <i32> [#uses=1]
|
||||
%tmp3 = and i32 1, %tmp29
|
||||
%tmp4 = icmp ne i32 %tmp3, 0 ; <i1> [#uses=1]
|
||||
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
|
||||
|
||||
bb: ; preds = %entry
|
||||
call void @foo()
|
||||
ret void
|
||||
|
||||
UnifiedReturnBlock: ; preds = %entry
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @atestne2(i32 %x, i32 %n) nounwind {
|
||||
entry:
|
||||
%tmp29 = ashr i32 %x, %n ; <i32> [#uses=1]
|
||||
%tmp3 = and i32 %tmp29, 1 ; <i32> [#uses=1]
|
||||
%tmp4 = icmp ne i32 %tmp3, 0 ; <i1> [#uses=1]
|
||||
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
|
||||
|
||||
bb: ; preds = %entry
|
||||
call void @foo()
|
||||
ret void
|
||||
|
||||
UnifiedReturnBlock: ; preds = %entry
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @atestne2b(i32 %x, i32 %n) nounwind {
|
||||
entry:
|
||||
%tmp29 = ashr i32 %x, %n ; <i32> [#uses=1]
|
||||
%tmp3 = and i32 1, %tmp29
|
||||
%tmp4 = icmp ne i32 %tmp3, 0 ; <i1> [#uses=1]
|
||||
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
|
||||
|
||||
bb: ; preds = %entry
|
||||
call void @foo()
|
||||
ret void
|
||||
|
||||
UnifiedReturnBlock: ; preds = %entry
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @testne3(i32 %x, i32 %n) nounwind {
|
||||
entry:
|
||||
%tmp29 = shl i32 1, %n ; <i32> [#uses=1]
|
||||
%tmp3 = and i32 %tmp29, %x ; <i32> [#uses=1]
|
||||
%tmp4 = icmp ne i32 %tmp3, 0 ; <i1> [#uses=1]
|
||||
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
|
||||
|
||||
bb: ; preds = %entry
|
||||
call void @foo()
|
||||
ret void
|
||||
|
||||
UnifiedReturnBlock: ; preds = %entry
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @testne3b(i32 %x, i32 %n) nounwind {
|
||||
entry:
|
||||
%tmp29 = shl i32 1, %n ; <i32> [#uses=1]
|
||||
%tmp3 = and i32 %x, %tmp29
|
||||
%tmp4 = icmp ne i32 %tmp3, 0 ; <i1> [#uses=1]
|
||||
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
|
||||
|
||||
bb: ; preds = %entry
|
||||
call void @foo()
|
||||
ret void
|
||||
|
||||
UnifiedReturnBlock: ; preds = %entry
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @query2(i32 %x, i32 %n) nounwind {
|
||||
entry:
|
||||
%tmp29 = lshr i32 %x, %n ; <i32> [#uses=1]
|
||||
%tmp3 = and i32 %tmp29, 1 ; <i32> [#uses=1]
|
||||
%tmp4 = icmp eq i32 %tmp3, 1 ; <i1> [#uses=1]
|
||||
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
|
||||
|
||||
bb: ; preds = %entry
|
||||
call void @foo()
|
||||
ret void
|
||||
|
||||
UnifiedReturnBlock: ; preds = %entry
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @query2b(i32 %x, i32 %n) nounwind {
|
||||
entry:
|
||||
%tmp29 = lshr i32 %x, %n ; <i32> [#uses=1]
|
||||
%tmp3 = and i32 1, %tmp29
|
||||
%tmp4 = icmp eq i32 %tmp3, 1 ; <i1> [#uses=1]
|
||||
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
|
||||
|
||||
bb: ; preds = %entry
|
||||
call void @foo()
|
||||
ret void
|
||||
|
||||
UnifiedReturnBlock: ; preds = %entry
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @aquery2(i32 %x, i32 %n) nounwind {
|
||||
entry:
|
||||
%tmp29 = ashr i32 %x, %n ; <i32> [#uses=1]
|
||||
%tmp3 = and i32 %tmp29, 1 ; <i32> [#uses=1]
|
||||
%tmp4 = icmp eq i32 %tmp3, 1 ; <i1> [#uses=1]
|
||||
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
|
||||
|
||||
bb: ; preds = %entry
|
||||
call void @foo()
|
||||
ret void
|
||||
|
||||
UnifiedReturnBlock: ; preds = %entry
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @aquery2b(i32 %x, i32 %n) nounwind {
|
||||
entry:
|
||||
%tmp29 = ashr i32 %x, %n ; <i32> [#uses=1]
|
||||
%tmp3 = and i32 1, %tmp29
|
||||
%tmp4 = icmp eq i32 %tmp3, 1 ; <i1> [#uses=1]
|
||||
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
|
||||
|
||||
bb: ; preds = %entry
|
||||
call void @foo()
|
||||
ret void
|
||||
|
||||
UnifiedReturnBlock: ; preds = %entry
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @query3(i32 %x, i32 %n) nounwind {
|
||||
entry:
|
||||
%tmp29 = shl i32 1, %n ; <i32> [#uses=1]
|
||||
%tmp3 = and i32 %tmp29, %x ; <i32> [#uses=1]
|
||||
%tmp4 = icmp eq i32 %tmp3, %tmp29 ; <i1> [#uses=1]
|
||||
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
|
||||
|
||||
bb: ; preds = %entry
|
||||
call void @foo()
|
||||
ret void
|
||||
|
||||
UnifiedReturnBlock: ; preds = %entry
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @query3b(i32 %x, i32 %n) nounwind {
|
||||
entry:
|
||||
%tmp29 = shl i32 1, %n ; <i32> [#uses=1]
|
||||
%tmp3 = and i32 %x, %tmp29
|
||||
%tmp4 = icmp eq i32 %tmp3, %tmp29 ; <i1> [#uses=1]
|
||||
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
|
||||
|
||||
bb: ; preds = %entry
|
||||
call void @foo()
|
||||
ret void
|
||||
|
||||
UnifiedReturnBlock: ; preds = %entry
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @query3x(i32 %x, i32 %n) nounwind {
|
||||
entry:
|
||||
%tmp29 = shl i32 1, %n ; <i32> [#uses=1]
|
||||
%tmp3 = and i32 %tmp29, %x ; <i32> [#uses=1]
|
||||
%tmp4 = icmp eq i32 %tmp29, %tmp3 ; <i1> [#uses=1]
|
||||
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
|
||||
|
||||
bb: ; preds = %entry
|
||||
call void @foo()
|
||||
ret void
|
||||
|
||||
UnifiedReturnBlock: ; preds = %entry
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @query3bx(i32 %x, i32 %n) nounwind {
|
||||
entry:
|
||||
%tmp29 = shl i32 1, %n ; <i32> [#uses=1]
|
||||
%tmp3 = and i32 %x, %tmp29
|
||||
%tmp4 = icmp eq i32 %tmp29, %tmp3 ; <i1> [#uses=1]
|
||||
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
|
||||
|
||||
bb: ; preds = %entry
|
||||
call void @foo()
|
||||
ret void
|
||||
|
||||
UnifiedReturnBlock: ; preds = %entry
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @queryne2(i32 %x, i32 %n) nounwind {
|
||||
entry:
|
||||
%tmp29 = lshr i32 %x, %n ; <i32> [#uses=1]
|
||||
%tmp3 = and i32 %tmp29, 1 ; <i32> [#uses=1]
|
||||
%tmp4 = icmp ne i32 %tmp3, 1 ; <i1> [#uses=1]
|
||||
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
|
||||
|
||||
bb: ; preds = %entry
|
||||
call void @foo()
|
||||
ret void
|
||||
|
||||
UnifiedReturnBlock: ; preds = %entry
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @queryne2b(i32 %x, i32 %n) nounwind {
|
||||
entry:
|
||||
%tmp29 = lshr i32 %x, %n ; <i32> [#uses=1]
|
||||
%tmp3 = and i32 1, %tmp29
|
||||
%tmp4 = icmp ne i32 %tmp3, 1 ; <i1> [#uses=1]
|
||||
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
|
||||
|
||||
bb: ; preds = %entry
|
||||
call void @foo()
|
||||
ret void
|
||||
|
||||
UnifiedReturnBlock: ; preds = %entry
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @aqueryne2(i32 %x, i32 %n) nounwind {
|
||||
entry:
|
||||
%tmp29 = ashr i32 %x, %n ; <i32> [#uses=1]
|
||||
%tmp3 = and i32 %tmp29, 1 ; <i32> [#uses=1]
|
||||
%tmp4 = icmp ne i32 %tmp3, 1 ; <i1> [#uses=1]
|
||||
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
|
||||
|
||||
bb: ; preds = %entry
|
||||
call void @foo()
|
||||
ret void
|
||||
|
||||
UnifiedReturnBlock: ; preds = %entry
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @aqueryne2b(i32 %x, i32 %n) nounwind {
|
||||
entry:
|
||||
%tmp29 = ashr i32 %x, %n ; <i32> [#uses=1]
|
||||
%tmp3 = and i32 1, %tmp29
|
||||
%tmp4 = icmp ne i32 %tmp3, 1 ; <i1> [#uses=1]
|
||||
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
|
||||
|
||||
bb: ; preds = %entry
|
||||
call void @foo()
|
||||
ret void
|
||||
|
||||
UnifiedReturnBlock: ; preds = %entry
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @queryne3(i32 %x, i32 %n) nounwind {
|
||||
entry:
|
||||
%tmp29 = shl i32 1, %n ; <i32> [#uses=1]
|
||||
%tmp3 = and i32 %tmp29, %x ; <i32> [#uses=1]
|
||||
%tmp4 = icmp ne i32 %tmp3, %tmp29 ; <i1> [#uses=1]
|
||||
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
|
||||
|
||||
bb: ; preds = %entry
|
||||
call void @foo()
|
||||
ret void
|
||||
|
||||
UnifiedReturnBlock: ; preds = %entry
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @queryne3b(i32 %x, i32 %n) nounwind {
|
||||
entry:
|
||||
%tmp29 = shl i32 1, %n ; <i32> [#uses=1]
|
||||
%tmp3 = and i32 %x, %tmp29
|
||||
%tmp4 = icmp ne i32 %tmp3, %tmp29 ; <i1> [#uses=1]
|
||||
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
|
||||
|
||||
bb: ; preds = %entry
|
||||
call void @foo()
|
||||
ret void
|
||||
|
||||
UnifiedReturnBlock: ; preds = %entry
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @queryne3x(i32 %x, i32 %n) nounwind {
|
||||
entry:
|
||||
%tmp29 = shl i32 1, %n ; <i32> [#uses=1]
|
||||
%tmp3 = and i32 %tmp29, %x ; <i32> [#uses=1]
|
||||
%tmp4 = icmp ne i32 %tmp29, %tmp3 ; <i1> [#uses=1]
|
||||
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
|
||||
|
||||
bb: ; preds = %entry
|
||||
call void @foo()
|
||||
ret void
|
||||
|
||||
UnifiedReturnBlock: ; preds = %entry
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @queryne3bx(i32 %x, i32 %n) nounwind {
|
||||
entry:
|
||||
%tmp29 = shl i32 1, %n ; <i32> [#uses=1]
|
||||
%tmp3 = and i32 %x, %tmp29
|
||||
%tmp4 = icmp ne i32 %tmp29, %tmp3 ; <i1> [#uses=1]
|
||||
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
|
||||
|
||||
bb: ; preds = %entry
|
||||
call void @foo()
|
||||
ret void
|
||||
|
||||
UnifiedReturnBlock: ; preds = %entry
|
||||
ret void
|
||||
}
|
||||
|
||||
declare void @foo()
|
||||
|
||||
@ -1,5 +1,20 @@
|
||||
; RUN: llvm-as < %s | llc -march=x86 | grep {cmove 16(%esp)}
|
||||
; RUN: llvm-as < %s | llc -march=x86 > %t
|
||||
; RUN: grep btl %t | count 2
|
||||
; RUN: grep cmov %t | count 2
|
||||
; RUN: not grep test %t
|
||||
; RUN: not grep set %t
|
||||
; RUN: not grep j %t
|
||||
; RUN: not grep cmovne %t
|
||||
; RUN: not grep cmove %t
|
||||
|
||||
define i32 @foo(i32 %x, i32 %n, i32 %w, i32 %v) nounwind readnone {
|
||||
entry:
|
||||
%0 = lshr i32 %x, %n ; <i32> [#uses=1]
|
||||
%1 = and i32 %0, 1 ; <i32> [#uses=1]
|
||||
%toBool = icmp eq i32 %1, 0 ; <i1> [#uses=1]
|
||||
%.0 = select i1 %toBool, i32 %v, i32 12 ; <i32> [#uses=1]
|
||||
ret i32 %.0
|
||||
}
|
||||
define i32 @bar(i32 %x, i32 %n, i32 %w, i32 %v) nounwind readnone {
|
||||
entry:
|
||||
%0 = lshr i32 %x, %n ; <i32> [#uses=1]
|
||||
|
||||
Loading…
Reference in New Issue
Block a user