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Add support for "ri" addressing modes where the immediate is a 14-bit field
which is shifted left two bits before use. Instructions like STD use this addressing mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26942 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -201,6 +201,20 @@ namespace {
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printOperand(MI, OpNo+1);
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O << ')';
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}
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void printMemRegImmShifted(const MachineInstr *MI, unsigned OpNo) {
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if (MI->getOperand(OpNo).isImmediate())
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printS16X4ImmOperand(MI, OpNo);
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else
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printSymbolLo(MI, OpNo);
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O << '(';
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if (MI->getOperand(OpNo+1).isRegister() &&
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MI->getOperand(OpNo+1).getReg() == PPC::R0)
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O << "0";
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else
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printOperand(MI, OpNo+1);
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O << ')';
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}
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void printMemRegReg(const MachineInstr *MI, unsigned OpNo) {
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// When used as the base register, r0 reads constant zero rather than
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// the value contained in the register. For this reason, the darwin
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@ -89,6 +89,11 @@ namespace {
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/// represented as an indexed [r+r] operation.
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bool SelectAddrIdxOnly(SDOperand N, SDOperand &Base, SDOperand &Index);
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/// SelectAddrImmShift - Returns true if the address N can be represented by
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/// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable
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/// for use by STD and friends.
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bool SelectAddrImmShift(SDOperand N, SDOperand &Disp, SDOperand &Base);
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/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
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/// inline asm expressions.
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virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
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@ -619,6 +624,82 @@ bool PPCDAGToDAGISel::SelectAddrIdxOnly(SDOperand N, SDOperand &Base,
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return true;
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}
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/// SelectAddrImmShift - Returns true if the address N can be represented by
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/// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable
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/// for use by STD and friends.
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bool PPCDAGToDAGISel::SelectAddrImmShift(SDOperand N, SDOperand &Disp,
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SDOperand &Base) {
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// If this can be more profitably realized as r+r, fail.
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if (SelectAddrIdx(N, Disp, Base))
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return false;
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if (N.getOpcode() == ISD::ADD) {
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unsigned imm = 0;
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if (isIntImmediate(N.getOperand(1), imm) && isInt16(imm) &&
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(imm & 3) == 0) {
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Disp = getI32Imm((imm & 0xFFFF) >> 2);
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if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
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Base = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
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} else {
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Base = N.getOperand(0);
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}
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return true; // [r+i]
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} else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
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// Match LOAD (ADD (X, Lo(G))).
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assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
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&& "Cannot handle constant offsets yet!");
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Disp = N.getOperand(1).getOperand(0); // The global address.
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assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
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Disp.getOpcode() == ISD::TargetConstantPool);
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Base = N.getOperand(0);
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return true; // [&g+r]
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}
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} else if (N.getOpcode() == ISD::OR) {
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unsigned imm = 0;
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if (isIntImmediate(N.getOperand(1), imm) && isInt16(imm) &&
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(imm & 3) == 0) {
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// If this is an or of disjoint bitfields, we can codegen this as an add
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// (for better address arithmetic) if the LHS and RHS of the OR are
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// provably disjoint.
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uint64_t LHSKnownZero, LHSKnownOne;
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PPCLowering.ComputeMaskedBits(N.getOperand(0), ~0U,
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LHSKnownZero, LHSKnownOne);
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if ((LHSKnownZero|~imm) == ~0U) {
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// If all of the bits are known zero on the LHS or RHS, the add won't
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// carry.
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Base = N.getOperand(0);
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Disp = getI32Imm((imm & 0xFFFF) >> 2);
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return true;
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}
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}
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} else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
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// Loading from a constant address.
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int Addr = (int)CN->getValue();
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if ((Addr & 3) == 0) {
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// If this address fits entirely in a 16-bit sext immediate field, codegen
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// this as "d, 0"
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if (Addr == (short)Addr) {
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Disp = getI32Imm(Addr >> 2);
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Base = CurDAG->getRegister(PPC::R0, MVT::i32);
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return true;
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}
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// Otherwise, break this down into an LIS + disp.
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Disp = getI32Imm((short)Addr >> 2);
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Base = CurDAG->getConstant(Addr - (signed short)Addr, MVT::i32);
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return true;
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}
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}
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Disp = getI32Imm(0);
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if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
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Base = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
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else
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Base = N;
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return true; // [r+0]
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}
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/// SelectCC - Select a comparison of the specified values with the specified
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/// condition code, returning the CR# of the expression.
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SDOperand PPCDAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS,
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