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Some SELECT_CC cleanups:
1. move assertions for node creation to getNode() 2. legalize the values returned in ExpandOp immediately 3. Move select_cc optimizations from SELECT's getNode() to SELECT_CC's, allowing them to be cleaned up significantly. This paves the way to pick up additional optimizations on SELECT_CC, such as sum-of-absolute-differences. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22757 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -190,10 +190,6 @@ public:
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SDOperand getSelectCC(SDOperand LHS, SDOperand RHS,
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SDOperand True, SDOperand False, ISD::CondCode Cond) {
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MVT::ValueType VT = True.getValueType();
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assert(LHS.getValueType() == RHS.getValueType() &&
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"LHS and RHS of condition must have same type!");
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assert(True.getValueType() == False.getValueType() &&
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"True and False arms of SelectCC must have same type!");
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return getNode(ISD::SELECT_CC, VT, LHS, RHS, True, False,getCondCode(Cond));
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}
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@ -2782,6 +2782,8 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
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Node->getOperand(1), TL, FL, Node->getOperand(4));
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Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
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Node->getOperand(1), TH, FH, Node->getOperand(4));
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Lo = LegalizeOp(Lo);
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Hi = LegalizeOp(Hi);
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break;
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}
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case ISD::SIGN_EXTEND: {
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@ -1397,59 +1397,6 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
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if (N1 == N3) // X ? Y : X --> X ? Y : 0 --> X & Y
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return getNode(ISD::AND, VT, N1, N2);
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}
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// If this is a selectcc, check to see if we can simplify the result.
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if (N1.Val->getOpcode() == ISD::SETCC) {
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SDNode *SetCC = N1.Val;
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ISD::CondCode CC = cast<CondCodeSDNode>(SetCC->getOperand(2))->get();
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if (ConstantFPSDNode *CFP =
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dyn_cast<ConstantFPSDNode>(SetCC->getOperand(1)))
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if (CFP->getValue() == 0.0) { // Allow either -0.0 or 0.0
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// select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
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if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
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N2 == SetCC->getOperand(0) && N3.getOpcode() == ISD::FNEG &&
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N3.getOperand(0) == N2)
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return getNode(ISD::FABS, VT, N2);
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// select (setl[te] X, +/-0.0), fneg(X), X -> fabs
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if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
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N3 == SetCC->getOperand(0) && N2.getOpcode() == ISD::FNEG &&
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N2.getOperand(0) == N3)
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return getNode(ISD::FABS, VT, N3);
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}
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// select (setlt X, 0), A, 0 -> and (sra X, size(X)-1), A
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if (ConstantSDNode *CN =
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dyn_cast<ConstantSDNode>(SetCC->getOperand(1)))
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if (CN->getValue() == 0 && N3C && N3C->getValue() == 0)
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if (CC == ISD::SETLT) {
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MVT::ValueType XType = SetCC->getOperand(0).getValueType();
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MVT::ValueType AType = N2.getValueType();
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if (XType >= AType) {
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// and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
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// single-bit constant. FIXME: remove once the dag combiner
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// exists.
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if (ConstantSDNode *AC = dyn_cast<ConstantSDNode>(N2))
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if ((AC->getValue() & (AC->getValue()-1)) == 0) {
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unsigned ShCtV = Log2_64(AC->getValue());
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ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
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SDOperand ShCt = getConstant(ShCtV, TLI.getShiftAmountTy());
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SDOperand Shift = getNode(ISD::SRL, XType,
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SetCC->getOperand(0), ShCt);
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if (XType > AType)
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Shift = getNode(ISD::TRUNCATE, AType, Shift);
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return getNode(ISD::AND, AType, Shift, N2);
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}
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SDOperand Shift = getNode(ISD::SRA, XType, SetCC->getOperand(0),
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getConstant(MVT::getSizeInBits(XType)-1,
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TLI.getShiftAmountTy()));
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if (XType > AType)
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Shift = getNode(ISD::TRUNCATE, AType, Shift);
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return getNode(ISD::AND, AType, Shift, N2);
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}
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}
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}
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break;
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case ISD::BRCOND:
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if (N2C)
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@ -1491,6 +1438,65 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
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SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
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SDOperand N1, SDOperand N2, SDOperand N3,
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SDOperand N4, SDOperand N5) {
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if (ISD::SELECT_CC == Opcode) {
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assert(N1.getValueType() == N2.getValueType() &&
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"LHS and RHS of condition must have same type!");
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assert(N3.getValueType() == N4.getValueType() &&
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"True and False arms of SelectCC must have same type!");
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ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
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ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
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ConstantSDNode *N4C = dyn_cast<ConstantSDNode>(N4.Val);
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ISD::CondCode CC = cast<CondCodeSDNode>(N5)->get();
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// Check to see if we can simplify the select into an fabs node
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if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N2)) {
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// Allow either -0.0 or 0.0
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if (CFP->getValue() == 0.0) {
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// select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
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if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
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N1 == N3 && N4.getOpcode() == ISD::FNEG &&
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N1 == N4.getOperand(0))
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return getNode(ISD::FABS, VT, N1);
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// select (setl[te] X, +/-0.0), fneg(X), X -> fabs
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if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
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N1 == N4 && N3.getOpcode() == ISD::FNEG &&
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N3.getOperand(0) == N4)
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return getNode(ISD::FABS, VT, N4);
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}
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}
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// Check to see if we can perform the "gzip trick", transforming
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// select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
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if (N2C && N2C->isNullValue() && N4C && N4C->isNullValue() &&
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MVT::isInteger(N1.getValueType()) &&
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MVT::isInteger(N3.getValueType()) && CC == ISD::SETLT) {
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MVT::ValueType XType = N1.getValueType();
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MVT::ValueType AType = N3.getValueType();
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if (XType >= AType) {
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// and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
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// single-bit constant. FIXME: remove once the dag combiner
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// exists.
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if (N3C && ((N3C->getValue() & (N3C->getValue()-1)) == 0)) {
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unsigned ShCtV = Log2_64(N3C->getValue());
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ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
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SDOperand ShCt = getConstant(ShCtV, TLI.getShiftAmountTy());
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SDOperand Shift = getNode(ISD::SRL, XType, N1, ShCt);
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if (XType > AType)
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Shift = getNode(ISD::TRUNCATE, AType, Shift);
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return getNode(ISD::AND, AType, Shift, N3);
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}
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SDOperand Shift = getNode(ISD::SRA, XType, N1,
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getConstant(MVT::getSizeInBits(XType)-1,
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TLI.getShiftAmountTy()));
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if (XType > AType)
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Shift = getNode(ISD::TRUNCATE, AType, Shift);
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return getNode(ISD::AND, AType, Shift, N3);
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}
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}
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}
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std::vector<SDOperand> Ops;
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Ops.reserve(5);
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Ops.push_back(N1);
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