mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-18 12:29:27 +00:00
Enabling new condition code modeling scheme.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42459 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
fb71392848
commit
e5f6204cd5
@ -73,11 +73,6 @@ namespace llvm {
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/// ExceptionHandling - This flag indicates that exception information should
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/// be emitted.
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extern bool ExceptionHandling;
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/// NewCCModeling - This temporary flag indicates whether to use the new
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/// condition code modeling scheme.
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extern bool NewCCModeling;
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} // End llvm namespace
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#endif
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@ -31,7 +31,6 @@ namespace llvm {
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bool UseSoftFloat;
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bool NoZerosInBSS;
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bool ExceptionHandling;
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bool NewCCModeling;
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Reloc::Model RelocationModel;
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CodeModel::Model CMModel;
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}
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@ -117,11 +116,6 @@ namespace {
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clEnumValN(CodeModel::Large, "large",
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" Large code model"),
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clEnumValEnd));
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cl::opt<bool, true>
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EnableNewCCModeling("new-cc-modeling-scheme",
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cl::desc("New CC modeling scheme."),
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cl::location(NewCCModeling),
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cl::init(false));
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}
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//---------------------------------------------------------------------------
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@ -437,39 +437,6 @@ static const TableEntry OpcodeTable[] = {
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{ X86::MUL_FpI32m32 , X86::MUL_FI32m },
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{ X86::MUL_FpI32m64 , X86::MUL_FI32m },
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{ X86::MUL_FpI32m80 , X86::MUL_FI32m },
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// TEMPORARY
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{ X86::NEW_CMOVBE_Fp32 , X86::CMOVBE_F },
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{ X86::NEW_CMOVBE_Fp64 , X86::CMOVBE_F },
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{ X86::NEW_CMOVBE_Fp80 , X86::CMOVBE_F },
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{ X86::NEW_CMOVB_Fp32 , X86::CMOVB_F },
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{ X86::NEW_CMOVB_Fp64 , X86::CMOVB_F },
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{ X86::NEW_CMOVB_Fp80 , X86::CMOVB_F },
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{ X86::NEW_CMOVE_Fp32 , X86::CMOVE_F },
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{ X86::NEW_CMOVE_Fp64 , X86::CMOVE_F },
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{ X86::NEW_CMOVE_Fp80 , X86::CMOVE_F },
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{ X86::NEW_CMOVNBE_Fp32 , X86::CMOVNBE_F },
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{ X86::NEW_CMOVNBE_Fp64 , X86::CMOVNBE_F },
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{ X86::NEW_CMOVNBE_Fp80 , X86::CMOVNBE_F },
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{ X86::NEW_CMOVNB_Fp32 , X86::CMOVNB_F },
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{ X86::NEW_CMOVNB_Fp64 , X86::CMOVNB_F },
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{ X86::NEW_CMOVNB_Fp80 , X86::CMOVNB_F },
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{ X86::NEW_CMOVNE_Fp32 , X86::CMOVNE_F },
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{ X86::NEW_CMOVNE_Fp64 , X86::CMOVNE_F },
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{ X86::NEW_CMOVNE_Fp80 , X86::CMOVNE_F },
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{ X86::NEW_CMOVNP_Fp32 , X86::CMOVNP_F },
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{ X86::NEW_CMOVNP_Fp64 , X86::CMOVNP_F },
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{ X86::NEW_CMOVNP_Fp80 , X86::CMOVNP_F },
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{ X86::NEW_CMOVP_Fp32 , X86::CMOVP_F },
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{ X86::NEW_CMOVP_Fp64 , X86::CMOVP_F },
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{ X86::NEW_CMOVP_Fp80 , X86::CMOVP_F },
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{ X86::NEW_UCOM_FpIr32 , X86::UCOM_FIr },
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{ X86::NEW_UCOM_FpIr64 , X86::UCOM_FIr },
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{ X86::NEW_UCOM_FpIr80 , X86::UCOM_FIr },
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{ X86::NEW_UCOM_Fpr32 , X86::UCOM_Fr },
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{ X86::NEW_UCOM_Fpr64 , X86::UCOM_Fr },
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{ X86::NEW_UCOM_Fpr80 , X86::UCOM_Fr },
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{ X86::SIN_Fp32 , X86::SIN_F },
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{ X86::SIN_Fp64 , X86::SIN_F },
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{ X86::SIN_Fp80 , X86::SIN_F },
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@ -3356,15 +3356,12 @@ SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) {
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const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
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SDOperand AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt,
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DAG.getConstant(32, MVT::i8));
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SDOperand COps[]={DAG.getEntryNode(), AndNode, DAG.getConstant(0, MVT::i8)};
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SDOperand Cond = NewCCModeling
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? DAG.getNode(X86ISD::CMP_NEW, MVT::i32,
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AndNode, DAG.getConstant(0, MVT::i8))
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: DAG.getNode(X86ISD::CMP, VTs, 2, COps, 3).getValue(1);
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SDOperand Cond = DAG.getNode(X86ISD::CMP, MVT::i32,
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AndNode, DAG.getConstant(0, MVT::i8));
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SDOperand Hi, Lo;
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SDOperand CC = DAG.getConstant(X86::COND_NE, MVT::i8);
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unsigned Opc = NewCCModeling ? X86ISD::CMOV_NEW : X86ISD::CMOV;
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unsigned Opc = X86ISD::CMOV;
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VTs = DAG.getNodeValueTypes(MVT::i32, MVT::Flag);
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SmallVector<SDOperand, 4> Ops;
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if (Op.getOpcode() == ISD::SHL_PARTS) {
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@ -3372,43 +3369,27 @@ SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) {
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Ops.push_back(Tmp3);
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Ops.push_back(CC);
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Ops.push_back(Cond);
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if (NewCCModeling)
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Hi = DAG.getNode(Opc, MVT::i32, &Ops[0], Ops.size());
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else {
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Hi = DAG.getNode(Opc, VTs, 2, &Ops[0], Ops.size());
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Cond = Hi.getValue(1);
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}
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Hi = DAG.getNode(Opc, MVT::i32, &Ops[0], Ops.size());
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Ops.clear();
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Ops.push_back(Tmp3);
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Ops.push_back(Tmp1);
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Ops.push_back(CC);
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Ops.push_back(Cond);
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if (NewCCModeling)
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Lo = DAG.getNode(Opc, MVT::i32, &Ops[0], Ops.size());
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else
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Lo = DAG.getNode(Opc, VTs, 2, &Ops[0], Ops.size());
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Lo = DAG.getNode(Opc, MVT::i32, &Ops[0], Ops.size());
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} else {
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Ops.push_back(Tmp2);
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Ops.push_back(Tmp3);
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Ops.push_back(CC);
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Ops.push_back(Cond);
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if (NewCCModeling)
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Lo = DAG.getNode(Opc, MVT::i32, &Ops[0], Ops.size());
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else {
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Lo = DAG.getNode(Opc, VTs, 2, &Ops[0], Ops.size());
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Cond = Lo.getValue(1);
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}
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Lo = DAG.getNode(Opc, MVT::i32, &Ops[0], Ops.size());
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Ops.clear();
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Ops.push_back(Tmp3);
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Ops.push_back(Tmp1);
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Ops.push_back(CC);
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Ops.push_back(Cond);
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if (NewCCModeling)
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Hi = DAG.getNode(Opc, MVT::i32, &Ops[0], Ops.size());
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else
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Hi = DAG.getNode(Opc, VTs, 2, &Ops[0], Ops.size());
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Hi = DAG.getNode(Opc, MVT::i32, &Ops[0], Ops.size());
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}
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VTs = DAG.getNodeValueTypes(MVT::i32, MVT::i32);
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@ -3674,54 +3655,7 @@ SDOperand X86TargetLowering::LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) {
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return DAG.getNode(X86ISD::FOR, VT, Val, SignBit);
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}
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SDOperand X86TargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG,
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SDOperand Chain) {
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assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
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SDOperand Cond;
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SDOperand Op0 = Op.getOperand(0);
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SDOperand Op1 = Op.getOperand(1);
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SDOperand CC = Op.getOperand(2);
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ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
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const MVT::ValueType *VTs1 = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
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const MVT::ValueType *VTs2 = DAG.getNodeValueTypes(MVT::i8, MVT::Flag);
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bool isFP = MVT::isFloatingPoint(Op.getOperand(1).getValueType());
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unsigned X86CC;
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if (translateX86CC(cast<CondCodeSDNode>(CC)->get(), isFP, X86CC,
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Op0, Op1, DAG)) {
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SDOperand Ops1[] = { Chain, Op0, Op1 };
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Cond = DAG.getNode(X86ISD::CMP, VTs1, 2, Ops1, 3).getValue(1);
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SDOperand Ops2[] = { DAG.getConstant(X86CC, MVT::i8), Cond };
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return DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2);
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}
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assert(isFP && "Illegal integer SetCC!");
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SDOperand COps[] = { Chain, Op0, Op1 };
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Cond = DAG.getNode(X86ISD::CMP, VTs1, 2, COps, 3).getValue(1);
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switch (SetCCOpcode) {
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default: assert(false && "Illegal floating point SetCC!");
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case ISD::SETOEQ: { // !PF & ZF
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SDOperand Ops1[] = { DAG.getConstant(X86::COND_NP, MVT::i8), Cond };
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SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops1, 2);
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SDOperand Ops2[] = { DAG.getConstant(X86::COND_E, MVT::i8),
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Tmp1.getValue(1) };
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SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2);
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return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
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}
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case ISD::SETUNE: { // PF | !ZF
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SDOperand Ops1[] = { DAG.getConstant(X86::COND_P, MVT::i8), Cond };
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SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops1, 2);
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SDOperand Ops2[] = { DAG.getConstant(X86::COND_NE, MVT::i8),
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Tmp1.getValue(1) };
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SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2);
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return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
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}
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}
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}
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SDOperand X86TargetLowering::LowerSETCC_New(SDOperand Op, SelectionDAG &DAG) {
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SDOperand X86TargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
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assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
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SDOperand Cond;
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SDOperand Op0 = Op.getOperand(0);
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@ -3733,27 +3667,27 @@ SDOperand X86TargetLowering::LowerSETCC_New(SDOperand Op, SelectionDAG &DAG) {
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if (translateX86CC(cast<CondCodeSDNode>(CC)->get(), isFP, X86CC,
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Op0, Op1, DAG)) {
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Cond = DAG.getNode(X86ISD::CMP_NEW, MVT::i32, Op0, Op1);
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return DAG.getNode(X86ISD::SETCC_NEW, MVT::i8,
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Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Op0, Op1);
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return DAG.getNode(X86ISD::SETCC, MVT::i8,
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DAG.getConstant(X86CC, MVT::i8), Cond);
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}
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assert(isFP && "Illegal integer SetCC!");
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Cond = DAG.getNode(X86ISD::CMP_NEW, MVT::i32, Op0, Op1);
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Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Op0, Op1);
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switch (SetCCOpcode) {
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default: assert(false && "Illegal floating point SetCC!");
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case ISD::SETOEQ: { // !PF & ZF
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SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC_NEW, MVT::i8,
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SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, MVT::i8,
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DAG.getConstant(X86::COND_NP, MVT::i8), Cond);
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SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC_NEW, MVT::i8,
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SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
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DAG.getConstant(X86::COND_E, MVT::i8), Cond);
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return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
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}
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case ISD::SETUNE: { // PF | !ZF
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SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC_NEW, MVT::i8,
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SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, MVT::i8,
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DAG.getConstant(X86::COND_P, MVT::i8), Cond);
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SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC_NEW, MVT::i8,
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SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
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DAG.getConstant(X86::COND_NE, MVT::i8), Cond);
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return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
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}
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@ -3763,13 +3697,11 @@ SDOperand X86TargetLowering::LowerSETCC_New(SDOperand Op, SelectionDAG &DAG) {
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SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) {
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bool addTest = true;
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SDOperand Chain = DAG.getEntryNode();
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SDOperand Cond = Op.getOperand(0);
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SDOperand CC;
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const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
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if (Cond.getOpcode() == ISD::SETCC)
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Cond = LowerSETCC(Cond, DAG, Chain);
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Cond = LowerSETCC(Cond, DAG);
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if (Cond.getOpcode() == X86ISD::SETCC) {
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CC = Cond.getOperand(0);
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@ -3786,58 +3718,9 @@ SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) {
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! ((X86ScalarSSEf32 && Op.getValueType()==MVT::f32) ||
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(X86ScalarSSEf64 && Op.getValueType()==MVT::f64)) &&
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!hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
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if ((Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) &&
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!IllegalFPCMov) {
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SDOperand Ops[] = { Chain, Cmp.getOperand(1), Cmp.getOperand(2) };
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Cond = DAG.getNode(Opc, VTs, 2, Ops, 3);
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addTest = false;
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}
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}
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if (addTest) {
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CC = DAG.getConstant(X86::COND_NE, MVT::i8);
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SDOperand Ops[] = { Chain, Cond, DAG.getConstant(0, MVT::i8) };
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Cond = DAG.getNode(X86ISD::CMP, VTs, 2, Ops, 3);
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}
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VTs = DAG.getNodeValueTypes(Op.getValueType(), MVT::Flag);
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SmallVector<SDOperand, 4> Ops;
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// X86ISD::CMOV means set the result (which is operand 1) to the RHS if
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// condition is true.
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Ops.push_back(Op.getOperand(2));
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Ops.push_back(Op.getOperand(1));
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Ops.push_back(CC);
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Ops.push_back(Cond.getValue(1));
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return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
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}
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SDOperand X86TargetLowering::LowerSELECT_New(SDOperand Op, SelectionDAG &DAG) {
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bool addTest = true;
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SDOperand Cond = Op.getOperand(0);
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SDOperand CC;
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if (Cond.getOpcode() == ISD::SETCC)
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Cond = LowerSETCC_New(Cond, DAG);
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if (Cond.getOpcode() == X86ISD::SETCC_NEW) {
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CC = Cond.getOperand(0);
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// If condition flag is set by a X86ISD::CMP, then make a copy of it
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// (since flag operand cannot be shared). Use it as the condition setting
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// operand in place of the X86ISD::SETCC.
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// If the X86ISD::SETCC has more than one use, then perhaps it's better
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// to use a test instead of duplicating the X86ISD::CMP (for register
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// pressure reason)?
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SDOperand Cmp = Cond.getOperand(1);
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unsigned Opc = Cmp.getOpcode();
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bool IllegalFPCMov =
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! ((X86ScalarSSEf32 && Op.getValueType()==MVT::f32) ||
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(X86ScalarSSEf64 && Op.getValueType()==MVT::f64)) &&
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!hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
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if ((Opc == X86ISD::CMP_NEW ||
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Opc == X86ISD::COMI_NEW ||
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Opc == X86ISD::UCOMI_NEW) &&
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!IllegalFPCMov) {
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if ((Opc == X86ISD::CMP ||
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Opc == X86ISD::COMI ||
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Opc == X86ISD::UCOMI) && !IllegalFPCMov) {
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Cond = DAG.getNode(Opc, MVT::i32, Cmp.getOperand(0), Cmp.getOperand(1));
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addTest = false;
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}
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@ -3845,7 +3728,7 @@ SDOperand X86TargetLowering::LowerSELECT_New(SDOperand Op, SelectionDAG &DAG) {
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if (addTest) {
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CC = DAG.getConstant(X86::COND_NE, MVT::i8);
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Cond = DAG.getNode(X86ISD::CMP_NEW, MVT::i32, Cond,
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Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Cond,
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DAG.getConstant(0, MVT::i8));
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}
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@ -3858,7 +3741,7 @@ SDOperand X86TargetLowering::LowerSELECT_New(SDOperand Op, SelectionDAG &DAG) {
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Ops.push_back(Op.getOperand(1));
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Ops.push_back(CC);
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Ops.push_back(Cond);
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return DAG.getNode(X86ISD::CMOV_NEW, VTs, 2, &Ops[0], Ops.size());
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return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
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}
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SDOperand X86TargetLowering::LowerBRCOND(SDOperand Op, SelectionDAG &DAG) {
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@ -3867,10 +3750,9 @@ SDOperand X86TargetLowering::LowerBRCOND(SDOperand Op, SelectionDAG &DAG) {
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SDOperand Cond = Op.getOperand(1);
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SDOperand Dest = Op.getOperand(2);
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SDOperand CC;
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const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
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if (Cond.getOpcode() == ISD::SETCC)
|
||||
Cond = LowerSETCC(Cond, DAG, Chain);
|
||||
Cond = LowerSETCC(Cond, DAG);
|
||||
|
||||
if (Cond.getOpcode() == X86ISD::SETCC) {
|
||||
CC = Cond.getOperand(0);
|
||||
@ -3883,46 +3765,9 @@ SDOperand X86TargetLowering::LowerBRCOND(SDOperand Op, SelectionDAG &DAG) {
|
||||
// pressure reason)?
|
||||
SDOperand Cmp = Cond.getOperand(1);
|
||||
unsigned Opc = Cmp.getOpcode();
|
||||
if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) {
|
||||
SDOperand Ops[] = { Chain, Cmp.getOperand(1), Cmp.getOperand(2) };
|
||||
Cond = DAG.getNode(Opc, VTs, 2, Ops, 3);
|
||||
addTest = false;
|
||||
}
|
||||
}
|
||||
|
||||
if (addTest) {
|
||||
CC = DAG.getConstant(X86::COND_NE, MVT::i8);
|
||||
SDOperand Ops[] = { Chain, Cond, DAG.getConstant(0, MVT::i8) };
|
||||
Cond = DAG.getNode(X86ISD::CMP, VTs, 2, Ops, 3);
|
||||
}
|
||||
return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
|
||||
Cond, Op.getOperand(2), CC, Cond.getValue(1));
|
||||
}
|
||||
|
||||
SDOperand X86TargetLowering::LowerBRCOND_New(SDOperand Op, SelectionDAG &DAG) {
|
||||
bool addTest = true;
|
||||
SDOperand Chain = Op.getOperand(0);
|
||||
SDOperand Cond = Op.getOperand(1);
|
||||
SDOperand Dest = Op.getOperand(2);
|
||||
SDOperand CC;
|
||||
|
||||
if (Cond.getOpcode() == ISD::SETCC)
|
||||
Cond = LowerSETCC_New(Cond, DAG);
|
||||
|
||||
if (Cond.getOpcode() == X86ISD::SETCC_NEW) {
|
||||
CC = Cond.getOperand(0);
|
||||
|
||||
// If condition flag is set by a X86ISD::CMP, then make a copy of it
|
||||
// (since flag operand cannot be shared). Use it as the condition setting
|
||||
// operand in place of the X86ISD::SETCC.
|
||||
// If the X86ISD::SETCC has more than one use, then perhaps it's better
|
||||
// to use a test instead of duplicating the X86ISD::CMP (for register
|
||||
// pressure reason)?
|
||||
SDOperand Cmp = Cond.getOperand(1);
|
||||
unsigned Opc = Cmp.getOpcode();
|
||||
if (Opc == X86ISD::CMP_NEW ||
|
||||
Opc == X86ISD::COMI_NEW ||
|
||||
Opc == X86ISD::UCOMI_NEW) {
|
||||
if (Opc == X86ISD::CMP ||
|
||||
Opc == X86ISD::COMI ||
|
||||
Opc == X86ISD::UCOMI) {
|
||||
Cond = DAG.getNode(Opc, MVT::i32, Cmp.getOperand(0), Cmp.getOperand(1));
|
||||
addTest = false;
|
||||
}
|
||||
@ -3930,9 +3775,9 @@ SDOperand X86TargetLowering::LowerBRCOND_New(SDOperand Op, SelectionDAG &DAG) {
|
||||
|
||||
if (addTest) {
|
||||
CC = DAG.getConstant(X86::COND_NE, MVT::i8);
|
||||
Cond= DAG.getNode(X86ISD::CMP_NEW, MVT::i32, Cond, DAG.getConstant(0, MVT::i8));
|
||||
Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8));
|
||||
}
|
||||
return DAG.getNode(X86ISD::BRCOND_NEW, Op.getValueType(),
|
||||
return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
|
||||
Chain, Op.getOperand(2), CC, Cond);
|
||||
}
|
||||
|
||||
@ -4535,21 +4380,10 @@ X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
|
||||
SDOperand RHS = Op.getOperand(2);
|
||||
translateX86CC(CC, true, X86CC, LHS, RHS, DAG);
|
||||
|
||||
if (NewCCModeling) {
|
||||
Opc = (Opc == X86ISD::UCOMI) ? X86ISD::UCOMI_NEW : X86ISD::COMI_NEW;
|
||||
SDOperand Cond = DAG.getNode(Opc, MVT::i32, LHS, RHS);
|
||||
SDOperand SetCC = DAG.getNode(X86ISD::SETCC_NEW, MVT::i8,
|
||||
DAG.getConstant(X86CC, MVT::i8), Cond);
|
||||
return DAG.getNode(ISD::ANY_EXTEND, MVT::i32, SetCC);
|
||||
} else {
|
||||
const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
|
||||
SDOperand Ops1[] = { DAG.getEntryNode(), LHS, RHS };
|
||||
SDOperand Cond = DAG.getNode(Opc, VTs, 2, Ops1, 3);
|
||||
VTs = DAG.getNodeValueTypes(MVT::i8, MVT::Flag);
|
||||
SDOperand Ops2[] = { DAG.getConstant(X86CC, MVT::i8), Cond };
|
||||
SDOperand SetCC = DAG.getNode(X86ISD::SETCC, VTs, 2, Ops2, 2);
|
||||
return DAG.getNode(ISD::ANY_EXTEND, MVT::i32, SetCC);
|
||||
}
|
||||
SDOperand Cond = DAG.getNode(Opc, MVT::i32, LHS, RHS);
|
||||
SDOperand SetCC = DAG.getNode(X86ISD::SETCC, MVT::i8,
|
||||
DAG.getConstant(X86CC, MVT::i8), Cond);
|
||||
return DAG.getNode(ISD::ANY_EXTEND, MVT::i32, SetCC);
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -4721,15 +4555,9 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
|
||||
case ISD::FABS: return LowerFABS(Op, DAG);
|
||||
case ISD::FNEG: return LowerFNEG(Op, DAG);
|
||||
case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
|
||||
case ISD::SETCC: return NewCCModeling
|
||||
? LowerSETCC_New(Op, DAG)
|
||||
: LowerSETCC(Op, DAG, DAG.getEntryNode());
|
||||
case ISD::SELECT: return NewCCModeling
|
||||
? LowerSELECT_New(Op, DAG)
|
||||
: LowerSELECT(Op, DAG);
|
||||
case ISD::BRCOND: return NewCCModeling
|
||||
? LowerBRCOND_New(Op, DAG)
|
||||
: LowerBRCOND(Op, DAG);
|
||||
case ISD::SETCC: return LowerSETCC(Op, DAG);
|
||||
case ISD::SELECT: return LowerSELECT(Op, DAG);
|
||||
case ISD::BRCOND: return LowerBRCOND(Op, DAG);
|
||||
case ISD::JumpTable: return LowerJumpTable(Op, DAG);
|
||||
case ISD::CALL: return LowerCALL(Op, DAG);
|
||||
case ISD::RET: return LowerRET(Op, DAG);
|
||||
@ -4773,17 +4601,11 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
|
||||
case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
|
||||
case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
|
||||
case X86ISD::CMP: return "X86ISD::CMP";
|
||||
case X86ISD::CMP_NEW: return "X86ISD::CMP_NEW";
|
||||
case X86ISD::COMI: return "X86ISD::COMI";
|
||||
case X86ISD::COMI_NEW: return "X86ISD::COMI_NEW";
|
||||
case X86ISD::UCOMI: return "X86ISD::UCOMI";
|
||||
case X86ISD::UCOMI_NEW: return "X86ISD::UCOMI_NEW";
|
||||
case X86ISD::SETCC: return "X86ISD::SETCC";
|
||||
case X86ISD::SETCC_NEW: return "X86ISD::SETCC_NEW";
|
||||
case X86ISD::CMOV: return "X86ISD::CMOV";
|
||||
case X86ISD::CMOV_NEW: return "X86ISD::CMOV_NEW";
|
||||
case X86ISD::BRCOND: return "X86ISD::BRCOND";
|
||||
case X86ISD::BRCOND_NEW: return "X86ISD::BRCOND_NEW";
|
||||
case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
|
||||
case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
|
||||
case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
|
||||
@ -4902,13 +4724,7 @@ X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
|
||||
case X86::CMOV_FR64:
|
||||
case X86::CMOV_V4F32:
|
||||
case X86::CMOV_V2F64:
|
||||
case X86::CMOV_V2I64:
|
||||
|
||||
case X86::NEW_CMOV_FR32:
|
||||
case X86::NEW_CMOV_FR64:
|
||||
case X86::NEW_CMOV_V4F32:
|
||||
case X86::NEW_CMOV_V2F64:
|
||||
case X86::NEW_CMOV_V2I64: {
|
||||
case X86::CMOV_V2I64: {
|
||||
// To "insert" a SELECT_CC instruction, we actually have to insert the
|
||||
// diamond control-flow pattern. The incoming instruction knows the
|
||||
// destination vreg to set, the condition code register to branch on, the
|
||||
@ -5065,7 +4881,6 @@ void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
|
||||
switch (Opc) {
|
||||
default: break;
|
||||
case X86ISD::SETCC:
|
||||
case X86ISD::SETCC_NEW:
|
||||
KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL);
|
||||
break;
|
||||
}
|
||||
|
||||
@ -117,26 +117,22 @@ namespace llvm {
|
||||
|
||||
/// X86 compare and logical compare instructions.
|
||||
CMP, COMI, UCOMI,
|
||||
CMP_NEW, COMI_NEW, UCOMI_NEW,
|
||||
|
||||
/// X86 SetCC. Operand 1 is condition code, and operand 2 is the flag
|
||||
/// operand produced by a CMP instruction.
|
||||
SETCC,
|
||||
SETCC_NEW,
|
||||
|
||||
/// X86 conditional moves. Operand 1 and operand 2 are the two values
|
||||
/// to select from (operand 1 is a R/W operand). Operand 3 is the
|
||||
/// condition code, and operand 4 is the flag operand produced by a CMP
|
||||
/// or TEST instruction. It also writes a flag result.
|
||||
CMOV,
|
||||
CMOV_NEW,
|
||||
|
||||
/// X86 conditional branches. Operand 1 is the chain operand, operand 2
|
||||
/// is the block to branch if condition is true, operand 3 is the
|
||||
/// condition code, and operand 4 is the flag operand produced by a CMP
|
||||
/// or TEST instruction.
|
||||
BRCOND,
|
||||
BRCOND_NEW,
|
||||
|
||||
/// Return with a flag operand. Operand 1 is the chain operand, operand
|
||||
/// 2 is the number of bytes of stack to pop.
|
||||
@ -430,12 +426,9 @@ namespace llvm {
|
||||
SDOperand LowerFABS(SDOperand Op, SelectionDAG &DAG);
|
||||
SDOperand LowerFNEG(SDOperand Op, SelectionDAG &DAG);
|
||||
SDOperand LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG);
|
||||
SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG, SDOperand Chain);
|
||||
SDOperand LowerSETCC_New(SDOperand Op, SelectionDAG &DAG);
|
||||
SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG);
|
||||
SDOperand LowerSELECT(SDOperand Op, SelectionDAG &DAG);
|
||||
SDOperand LowerSELECT_New(SDOperand Op, SelectionDAG &DAG);
|
||||
SDOperand LowerBRCOND(SDOperand Op, SelectionDAG &DAG);
|
||||
SDOperand LowerBRCOND_New(SDOperand Op, SelectionDAG &DAG);
|
||||
SDOperand LowerMEMSET(SDOperand Op, SelectionDAG &DAG);
|
||||
SDOperand LowerMEMCPYInline(SDOperand Dest, SDOperand Source,
|
||||
SDOperand Chain, unsigned Size, unsigned Align,
|
||||
|
||||
@ -299,17 +299,20 @@ def TST_F : FPI<0xE4, RawFrm, (outs), (ins), "ftst">, D9;
|
||||
|
||||
// Floating point cmovs.
|
||||
multiclass FPCMov<PatLeaf cc> {
|
||||
def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), CondMovFP,
|
||||
def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2),
|
||||
CondMovFP,
|
||||
[(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2,
|
||||
cc))]>;
|
||||
def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), CondMovFP,
|
||||
cc, EFLAGS))]>;
|
||||
def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2),
|
||||
CondMovFP,
|
||||
[(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2,
|
||||
cc))]>;
|
||||
def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), CondMovFP,
|
||||
cc, EFLAGS))]>;
|
||||
def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2),
|
||||
CondMovFP,
|
||||
[(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2,
|
||||
cc))]>;
|
||||
cc, EFLAGS))]>;
|
||||
}
|
||||
let isTwoAddress = 1 in {
|
||||
let Uses = [EFLAGS], isTwoAddress = 1 in {
|
||||
defm CMOVB : FPCMov<X86_COND_B>;
|
||||
defm CMOVBE : FPCMov<X86_COND_BE>;
|
||||
defm CMOVE : FPCMov<X86_COND_E>;
|
||||
@ -320,31 +323,6 @@ defm CMOVNE : FPCMov<X86_COND_NE>;
|
||||
defm CMOVNP : FPCMov<X86_COND_NP>;
|
||||
}
|
||||
|
||||
multiclass NEW_FPCMov<PatLeaf cc> {
|
||||
def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2),
|
||||
CondMovFP,
|
||||
[(set RFP32:$dst, (X86cmov_new RFP32:$src1, RFP32:$src2,
|
||||
cc, EFLAGS))]>;
|
||||
def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2),
|
||||
CondMovFP,
|
||||
[(set RFP64:$dst, (X86cmov_new RFP64:$src1, RFP64:$src2,
|
||||
cc, EFLAGS))]>;
|
||||
def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2),
|
||||
CondMovFP,
|
||||
[(set RFP80:$dst, (X86cmov_new RFP80:$src1, RFP80:$src2,
|
||||
cc, EFLAGS))]>;
|
||||
}
|
||||
let Uses = [EFLAGS], isTwoAddress = 1 in {
|
||||
defm NEW_CMOVB : NEW_FPCMov<X86_COND_B>;
|
||||
defm NEW_CMOVBE : NEW_FPCMov<X86_COND_BE>;
|
||||
defm NEW_CMOVE : NEW_FPCMov<X86_COND_E>;
|
||||
defm NEW_CMOVP : NEW_FPCMov<X86_COND_P>;
|
||||
defm NEW_CMOVNB : NEW_FPCMov<X86_COND_AE>;
|
||||
defm NEW_CMOVNBE: NEW_FPCMov<X86_COND_A>;
|
||||
defm NEW_CMOVNE : NEW_FPCMov<X86_COND_NE>;
|
||||
defm NEW_CMOVNP : NEW_FPCMov<X86_COND_NP>;
|
||||
}
|
||||
|
||||
// These are not factored because there's no clean way to pass DA/DB.
|
||||
def CMOVB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins),
|
||||
"fcmovb\t{$op, %st(0)|%ST(0), $op}">, DA;
|
||||
@ -507,30 +485,17 @@ let Defs = [EFLAGS] in {
|
||||
def UCOM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
|
||||
[]>; // FPSW = cmp ST(0) with ST(i)
|
||||
def UCOM_FpIr32: FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
|
||||
[(X86cmp RFP32:$lhs, RFP32:$rhs)]>; // CC = ST(0) cmp ST(i)
|
||||
[(X86cmp RFP32:$lhs, RFP32:$rhs),
|
||||
(implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
|
||||
def UCOM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
|
||||
[]>; // FPSW = cmp ST(0) with ST(i)
|
||||
def UCOM_FpIr64: FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
|
||||
[(X86cmp RFP64:$lhs, RFP64:$rhs)]>; // CC = ST(0) cmp ST(i)
|
||||
[(X86cmp RFP64:$lhs, RFP64:$rhs),
|
||||
(implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
|
||||
def UCOM_Fpr80 : FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
|
||||
[]>; // FPSW = cmp ST(0) with ST(i)
|
||||
def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
|
||||
[(X86cmp RFP80:$lhs, RFP80:$rhs)]>; // CC = ST(0) cmp ST(i)
|
||||
|
||||
def NEW_UCOM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
|
||||
[]>; // FPSW = cmp ST(0) with ST(i)
|
||||
def NEW_UCOM_FpIr32: FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
|
||||
[(X86cmp_new RFP32:$lhs, RFP32:$rhs),
|
||||
(implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
|
||||
def NEW_UCOM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
|
||||
[]>; // FPSW = cmp ST(0) with ST(i)
|
||||
def NEW_UCOM_FpIr64: FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
|
||||
[(X86cmp_new RFP64:$lhs, RFP64:$rhs),
|
||||
(implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
|
||||
def NEW_UCOM_Fpr80 : FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
|
||||
[]>; // FPSW = cmp ST(0) with ST(i)
|
||||
def NEW_UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
|
||||
[(X86cmp_new RFP80:$lhs, RFP80:$rhs),
|
||||
[(X86cmp RFP80:$lhs, RFP80:$rhs),
|
||||
(implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
|
||||
}
|
||||
|
||||
|
||||
@ -386,68 +386,28 @@ static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
|
||||
case X86::JNP: return X86::COND_NP;
|
||||
case X86::JO: return X86::COND_O;
|
||||
case X86::JNO: return X86::COND_NO;
|
||||
// TEMPORARY
|
||||
case X86::NEW_JE: return X86::COND_E;
|
||||
case X86::NEW_JNE: return X86::COND_NE;
|
||||
case X86::NEW_JL: return X86::COND_L;
|
||||
case X86::NEW_JLE: return X86::COND_LE;
|
||||
case X86::NEW_JG: return X86::COND_G;
|
||||
case X86::NEW_JGE: return X86::COND_GE;
|
||||
case X86::NEW_JB: return X86::COND_B;
|
||||
case X86::NEW_JBE: return X86::COND_BE;
|
||||
case X86::NEW_JA: return X86::COND_A;
|
||||
case X86::NEW_JAE: return X86::COND_AE;
|
||||
case X86::NEW_JS: return X86::COND_S;
|
||||
case X86::NEW_JNS: return X86::COND_NS;
|
||||
case X86::NEW_JP: return X86::COND_P;
|
||||
case X86::NEW_JNP: return X86::COND_NP;
|
||||
case X86::NEW_JO: return X86::COND_O;
|
||||
case X86::NEW_JNO: return X86::COND_NO;
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
|
||||
if (!NewCCModeling) {
|
||||
switch (CC) {
|
||||
default: assert(0 && "Illegal condition code!");
|
||||
case X86::COND_E: return X86::JE;
|
||||
case X86::COND_NE: return X86::JNE;
|
||||
case X86::COND_L: return X86::JL;
|
||||
case X86::COND_LE: return X86::JLE;
|
||||
case X86::COND_G: return X86::JG;
|
||||
case X86::COND_GE: return X86::JGE;
|
||||
case X86::COND_B: return X86::JB;
|
||||
case X86::COND_BE: return X86::JBE;
|
||||
case X86::COND_A: return X86::JA;
|
||||
case X86::COND_AE: return X86::JAE;
|
||||
case X86::COND_S: return X86::JS;
|
||||
case X86::COND_NS: return X86::JNS;
|
||||
case X86::COND_P: return X86::JP;
|
||||
case X86::COND_NP: return X86::JNP;
|
||||
case X86::COND_O: return X86::JO;
|
||||
case X86::COND_NO: return X86::JNO;
|
||||
}
|
||||
}
|
||||
|
||||
switch (CC) {
|
||||
default: assert(0 && "Illegal condition code!");
|
||||
case X86::COND_E: return X86::NEW_JE;
|
||||
case X86::COND_NE: return X86::NEW_JNE;
|
||||
case X86::COND_L: return X86::NEW_JL;
|
||||
case X86::COND_LE: return X86::NEW_JLE;
|
||||
case X86::COND_G: return X86::NEW_JG;
|
||||
case X86::COND_GE: return X86::NEW_JGE;
|
||||
case X86::COND_B: return X86::NEW_JB;
|
||||
case X86::COND_BE: return X86::NEW_JBE;
|
||||
case X86::COND_A: return X86::NEW_JA;
|
||||
case X86::COND_AE: return X86::NEW_JAE;
|
||||
case X86::COND_S: return X86::NEW_JS;
|
||||
case X86::COND_NS: return X86::NEW_JNS;
|
||||
case X86::COND_P: return X86::NEW_JP;
|
||||
case X86::COND_NP: return X86::NEW_JNP;
|
||||
case X86::COND_O: return X86::NEW_JO;
|
||||
case X86::COND_NO: return X86::NEW_JNO;
|
||||
case X86::COND_E: return X86::JE;
|
||||
case X86::COND_NE: return X86::JNE;
|
||||
case X86::COND_L: return X86::JL;
|
||||
case X86::COND_LE: return X86::JLE;
|
||||
case X86::COND_G: return X86::JG;
|
||||
case X86::COND_GE: return X86::JGE;
|
||||
case X86::COND_B: return X86::JB;
|
||||
case X86::COND_BE: return X86::JBE;
|
||||
case X86::COND_A: return X86::JA;
|
||||
case X86::COND_AE: return X86::JAE;
|
||||
case X86::COND_S: return X86::JS;
|
||||
case X86::COND_NS: return X86::JNS;
|
||||
case X86::COND_P: return X86::JP;
|
||||
case X86::COND_NP: return X86::JNP;
|
||||
case X86::COND_O: return X86::JO;
|
||||
case X86::COND_NO: return X86::JNO;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -33,12 +33,8 @@ def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
|
||||
def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
|
||||
def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
|
||||
def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest,
|
||||
[SDNPHasChain, SDNPOutFlag]>;
|
||||
def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest,
|
||||
[SDNPHasChain, SDNPOutFlag]>;
|
||||
def X86comi_new: SDNode<"X86ISD::COMI_NEW", SDTX86CmpTest,
|
||||
[SDNPHasChain]>;
|
||||
def X86ucomi_new: SDNode<"X86ISD::UCOMI_NEW",SDTX86CmpTest>;
|
||||
def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
|
||||
def X86s2vec : SDNode<"X86ISD::S2VEC", SDTypeProfile<1, 1, []>, []>;
|
||||
def X86pextrw : SDNode<"X86ISD::PEXTRW", SDTypeProfile<1, 2, []>, []>;
|
||||
def X86pinsrw : SDNode<"X86ISD::PINSRW", SDTypeProfile<1, 3, []>, []>;
|
||||
@ -271,54 +267,30 @@ let Uses = [EFLAGS], usesCustomDAGSchedInserter = 1 in {
|
||||
def CMOV_FR32 : I<0, Pseudo,
|
||||
(outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
|
||||
"#CMOV_FR32 PSEUDO!",
|
||||
[(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond))]>;
|
||||
[(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
|
||||
EFLAGS))]>;
|
||||
def CMOV_FR64 : I<0, Pseudo,
|
||||
(outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
|
||||
"#CMOV_FR64 PSEUDO!",
|
||||
[(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond))]>;
|
||||
[(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
|
||||
EFLAGS))]>;
|
||||
def CMOV_V4F32 : I<0, Pseudo,
|
||||
(outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
|
||||
"#CMOV_V4F32 PSEUDO!",
|
||||
[(set VR128:$dst,
|
||||
(v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
|
||||
(v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
|
||||
EFLAGS)))]>;
|
||||
def CMOV_V2F64 : I<0, Pseudo,
|
||||
(outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
|
||||
"#CMOV_V2F64 PSEUDO!",
|
||||
[(set VR128:$dst,
|
||||
(v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
|
||||
(v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
|
||||
EFLAGS)))]>;
|
||||
def CMOV_V2I64 : I<0, Pseudo,
|
||||
(outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
|
||||
"#CMOV_V2I64 PSEUDO!",
|
||||
[(set VR128:$dst,
|
||||
(v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
|
||||
|
||||
def NEW_CMOV_FR32 : I<0, Pseudo,
|
||||
(outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
|
||||
"#CMOV_FR32 PSEUDO!",
|
||||
[(set FR32:$dst, (X86cmov_new FR32:$t, FR32:$f, imm:$cond,
|
||||
EFLAGS))]>;
|
||||
def NEW_CMOV_FR64 : I<0, Pseudo,
|
||||
(outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
|
||||
"#CMOV_FR64 PSEUDO!",
|
||||
[(set FR64:$dst, (X86cmov_new FR64:$t, FR64:$f, imm:$cond,
|
||||
EFLAGS))]>;
|
||||
def NEW_CMOV_V4F32 : I<0, Pseudo,
|
||||
(outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
|
||||
"#CMOV_V4F32 PSEUDO!",
|
||||
[(set VR128:$dst,
|
||||
(v4f32 (X86cmov_new VR128:$t, VR128:$f, imm:$cond,
|
||||
EFLAGS)))]>;
|
||||
def NEW_CMOV_V2F64 : I<0, Pseudo,
|
||||
(outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
|
||||
"#CMOV_V2F64 PSEUDO!",
|
||||
[(set VR128:$dst,
|
||||
(v2f64 (X86cmov_new VR128:$t, VR128:$f, imm:$cond,
|
||||
EFLAGS)))]>;
|
||||
def NEW_CMOV_V2I64 : I<0, Pseudo,
|
||||
(outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
|
||||
"#CMOV_V2I64 PSEUDO!",
|
||||
[(set VR128:$dst,
|
||||
(v2i64 (X86cmov_new VR128:$t, VR128:$f, imm:$cond,
|
||||
(v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
|
||||
EFLAGS)))]>;
|
||||
}
|
||||
|
||||
@ -396,17 +368,10 @@ let isTwoAddress = 1 in {
|
||||
let Defs = [EFLAGS] in {
|
||||
def UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins FR32:$src1, FR32:$src2),
|
||||
"ucomiss\t{$src2, $src1|$src1, $src2}",
|
||||
[(X86cmp FR32:$src1, FR32:$src2)]>;
|
||||
[(X86cmp FR32:$src1, FR32:$src2), (implicit EFLAGS)]>;
|
||||
def UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs), (ins FR32:$src1, f32mem:$src2),
|
||||
"ucomiss\t{$src2, $src1|$src1, $src2}",
|
||||
[(X86cmp FR32:$src1, (loadf32 addr:$src2))]>;
|
||||
|
||||
def NEW_UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins FR32:$src1, FR32:$src2),
|
||||
"ucomiss\t{$src2, $src1|$src1, $src2}",
|
||||
[(X86cmp_new FR32:$src1, FR32:$src2), (implicit EFLAGS)]>;
|
||||
def NEW_UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs), (ins FR32:$src1, f32mem:$src2),
|
||||
"ucomiss\t{$src2, $src1|$src1, $src2}",
|
||||
[(X86cmp_new FR32:$src1, (loadf32 addr:$src2)),
|
||||
[(X86cmp FR32:$src1, (loadf32 addr:$src2)),
|
||||
(implicit EFLAGS)]>;
|
||||
} // Defs = [EFLAGS]
|
||||
|
||||
@ -425,40 +390,26 @@ let isTwoAddress = 1 in {
|
||||
}
|
||||
|
||||
let Defs = [EFLAGS] in {
|
||||
def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
|
||||
"ucomiss\t{$src2, $src1|$src1, $src2}",
|
||||
[(X86ucomi (v4f32 VR128:$src1), VR128:$src2)]>;
|
||||
def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
|
||||
"ucomiss\t{$src2, $src1|$src1, $src2}",
|
||||
[(X86ucomi (v4f32 VR128:$src1), (load addr:$src2))]>;
|
||||
|
||||
def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
|
||||
"comiss\t{$src2, $src1|$src1, $src2}",
|
||||
[(X86comi (v4f32 VR128:$src1), VR128:$src2)]>;
|
||||
def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
|
||||
"comiss\t{$src2, $src1|$src1, $src2}",
|
||||
[(X86comi (v4f32 VR128:$src1), (load addr:$src2))]>;
|
||||
|
||||
def NEW_Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs),
|
||||
def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs),
|
||||
(ins VR128:$src1, VR128:$src2),
|
||||
"ucomiss\t{$src2, $src1|$src1, $src2}",
|
||||
[(X86ucomi_new (v4f32 VR128:$src1), VR128:$src2),
|
||||
[(X86ucomi (v4f32 VR128:$src1), VR128:$src2),
|
||||
(implicit EFLAGS)]>;
|
||||
def NEW_Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs),
|
||||
def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs),
|
||||
(ins VR128:$src1, f128mem:$src2),
|
||||
"ucomiss\t{$src2, $src1|$src1, $src2}",
|
||||
[(X86ucomi_new (v4f32 VR128:$src1), (load addr:$src2)),
|
||||
[(X86ucomi (v4f32 VR128:$src1), (load addr:$src2)),
|
||||
(implicit EFLAGS)]>;
|
||||
|
||||
def NEW_Int_COMISSrr: PSI<0x2F, MRMSrcReg, (outs),
|
||||
def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (outs),
|
||||
(ins VR128:$src1, VR128:$src2),
|
||||
"comiss\t{$src2, $src1|$src1, $src2}",
|
||||
[(X86comi_new (v4f32 VR128:$src1), VR128:$src2),
|
||||
[(X86comi (v4f32 VR128:$src1), VR128:$src2),
|
||||
(implicit EFLAGS)]>;
|
||||
def NEW_Int_COMISSrm: PSI<0x2F, MRMSrcMem, (outs),
|
||||
def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (outs),
|
||||
(ins VR128:$src1, f128mem:$src2),
|
||||
"comiss\t{$src2, $src1|$src1, $src2}",
|
||||
[(X86comi_new (v4f32 VR128:$src1), (load addr:$src2)),
|
||||
[(X86comi (v4f32 VR128:$src1), (load addr:$src2)),
|
||||
(implicit EFLAGS)]>;
|
||||
} // Defs = [EFLAGS]
|
||||
|
||||
@ -1095,17 +1046,10 @@ let isTwoAddress = 1 in {
|
||||
let Defs = [EFLAGS] in {
|
||||
def UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins FR64:$src1, FR64:$src2),
|
||||
"ucomisd\t{$src2, $src1|$src1, $src2}",
|
||||
[(X86cmp FR64:$src1, FR64:$src2)]>;
|
||||
[(X86cmp FR64:$src1, FR64:$src2), (implicit EFLAGS)]>;
|
||||
def UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs), (ins FR64:$src1, f64mem:$src2),
|
||||
"ucomisd\t{$src2, $src1|$src1, $src2}",
|
||||
[(X86cmp FR64:$src1, (loadf64 addr:$src2))]>;
|
||||
|
||||
def NEW_UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins FR64:$src1, FR64:$src2),
|
||||
"ucomisd\t{$src2, $src1|$src1, $src2}",
|
||||
[(X86cmp_new FR64:$src1, FR64:$src2), (implicit EFLAGS)]>;
|
||||
def NEW_UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs), (ins FR64:$src1, f64mem:$src2),
|
||||
"ucomisd\t{$src2, $src1|$src1, $src2}",
|
||||
[(X86cmp_new FR64:$src1, (loadf64 addr:$src2)),
|
||||
[(X86cmp FR64:$src1, (loadf64 addr:$src2)),
|
||||
(implicit EFLAGS)]>;
|
||||
}
|
||||
|
||||
@ -1126,38 +1070,20 @@ let isTwoAddress = 1 in {
|
||||
let Defs = [EFLAGS] in {
|
||||
def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
|
||||
"ucomisd\t{$src2, $src1|$src1, $src2}",
|
||||
[(X86ucomi (v2f64 VR128:$src1), (v2f64 VR128:$src2))]>;
|
||||
def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
|
||||
[(X86ucomi (v2f64 VR128:$src1), (v2f64 VR128:$src2)),
|
||||
(implicit EFLAGS)]>;
|
||||
def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
|
||||
"ucomisd\t{$src2, $src1|$src1, $src2}",
|
||||
[(X86ucomi (v2f64 VR128:$src1), (load addr:$src2))]>;
|
||||
[(X86ucomi (v2f64 VR128:$src1), (load addr:$src2)),
|
||||
(implicit EFLAGS)]>;
|
||||
|
||||
def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
|
||||
"comisd\t{$src2, $src1|$src1, $src2}",
|
||||
[(X86comi (v2f64 VR128:$src1), (v2f64 VR128:$src2))]>;
|
||||
[(X86comi (v2f64 VR128:$src1), (v2f64 VR128:$src2)),
|
||||
(implicit EFLAGS)]>;
|
||||
def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
|
||||
"comisd\t{$src2, $src1|$src1, $src2}",
|
||||
[(X86comi (v2f64 VR128:$src1), (load addr:$src2))]>;
|
||||
|
||||
def NEW_Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs),
|
||||
(ins VR128:$src1, VR128:$src2),
|
||||
"ucomisd\t{$src2, $src1|$src1, $src2}",
|
||||
[(X86ucomi_new (v2f64 VR128:$src1), (v2f64 VR128:$src2)),
|
||||
(implicit EFLAGS)]>;
|
||||
def NEW_Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs),
|
||||
(ins VR128:$src1, f128mem:$src2),
|
||||
"ucomisd\t{$src2, $src1|$src1, $src2}",
|
||||
[(X86ucomi_new (v2f64 VR128:$src1), (load addr:$src2)),
|
||||
(implicit EFLAGS)]>;
|
||||
|
||||
def NEW_Int_COMISDrr: PDI<0x2F, MRMSrcReg, (outs),
|
||||
(ins VR128:$src1, VR128:$src2),
|
||||
"comisd\t{$src2, $src1|$src1, $src2}",
|
||||
[(X86comi_new (v2f64 VR128:$src1), (v2f64 VR128:$src2)),
|
||||
(implicit EFLAGS)]>;
|
||||
def NEW_Int_COMISDrm: PDI<0x2F, MRMSrcMem, (outs),
|
||||
(ins VR128:$src1, f128mem:$src2),
|
||||
"comisd\t{$src2, $src1|$src1, $src2}",
|
||||
[(X86comi_new (v2f64 VR128:$src1), (load addr:$src2)),
|
||||
[(X86comi (v2f64 VR128:$src1), (load addr:$src2)),
|
||||
(implicit EFLAGS)]>;
|
||||
} // Defs = EFLAGS]
|
||||
|
||||
|
||||
@ -723,89 +723,51 @@ let Defs = [EFLAGS] in {
|
||||
let isCommutable = 1 in
|
||||
def TEST64rr : RI<0x85, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
|
||||
"test{q}\t{$src2, $src1|$src1, $src2}",
|
||||
[(X86cmp (and GR64:$src1, GR64:$src2), 0)]>;
|
||||
[(X86cmp (and GR64:$src1, GR64:$src2), 0),
|
||||
(implicit EFLAGS)]>;
|
||||
def TEST64rm : RI<0x85, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
|
||||
"test{q}\t{$src2, $src1|$src1, $src2}",
|
||||
[(X86cmp (and GR64:$src1, (loadi64 addr:$src2)), 0)]>;
|
||||
def TEST64ri32 : RIi32<0xF7, MRM0r, (outs), (ins GR64:$src1, i64i32imm:$src2),
|
||||
[(X86cmp (and GR64:$src1, (loadi64 addr:$src2)), 0),
|
||||
(implicit EFLAGS)]>;
|
||||
def TEST64ri32 : RIi32<0xF7, MRM0r, (outs),
|
||||
(ins GR64:$src1, i64i32imm:$src2),
|
||||
"test{q}\t{$src2, $src1|$src1, $src2}",
|
||||
[(X86cmp (and GR64:$src1, i64immSExt32:$src2), 0)]>;
|
||||
def TEST64mi32 : RIi32<0xF7, MRM0m, (outs), (ins i64mem:$src1, i64i32imm:$src2),
|
||||
[(X86cmp (and GR64:$src1, i64immSExt32:$src2), 0),
|
||||
(implicit EFLAGS)]>;
|
||||
def TEST64mi32 : RIi32<0xF7, MRM0m, (outs),
|
||||
(ins i64mem:$src1, i64i32imm:$src2),
|
||||
"test{q}\t{$src2, $src1|$src1, $src2}",
|
||||
[(X86cmp (and (loadi64 addr:$src1), i64immSExt32:$src2), 0)]>;
|
||||
[(X86cmp (and (loadi64 addr:$src1), i64immSExt32:$src2), 0),
|
||||
(implicit EFLAGS)]>;
|
||||
|
||||
def CMP64rr : RI<0x39, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
|
||||
"cmp{q}\t{$src2, $src1|$src1, $src2}",
|
||||
[(X86cmp GR64:$src1, GR64:$src2)]>;
|
||||
[(X86cmp GR64:$src1, GR64:$src2),
|
||||
(implicit EFLAGS)]>;
|
||||
def CMP64mr : RI<0x39, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
|
||||
"cmp{q}\t{$src2, $src1|$src1, $src2}",
|
||||
[(X86cmp (loadi64 addr:$src1), GR64:$src2)]>;
|
||||
[(X86cmp (loadi64 addr:$src1), GR64:$src2),
|
||||
(implicit EFLAGS)]>;
|
||||
def CMP64rm : RI<0x3B, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmp{q}\t{$src2, $src1|$src1, $src2}",
|
||||
[(X86cmp GR64:$src1, (loadi64 addr:$src2))]>;
|
||||
[(X86cmp GR64:$src1, (loadi64 addr:$src2)),
|
||||
(implicit EFLAGS)]>;
|
||||
def CMP64ri32 : RIi32<0x81, MRM7r, (outs), (ins GR64:$src1, i64i32imm:$src2),
|
||||
"cmp{q}\t{$src2, $src1|$src1, $src2}",
|
||||
[(X86cmp GR64:$src1, i64immSExt32:$src2)]>;
|
||||
def CMP64mi32 : RIi32<0x81, MRM7m, (outs), (ins i64mem:$src1, i64i32imm:$src2),
|
||||
"cmp{q}\t{$src2, $src1|$src1, $src2}",
|
||||
[(X86cmp (loadi64 addr:$src1), i64immSExt32:$src2)]>;
|
||||
def CMP64mi8 : RIi8<0x83, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
|
||||
"cmp{q}\t{$src2, $src1|$src1, $src2}",
|
||||
[(X86cmp (loadi64 addr:$src1), i64immSExt8:$src2)]>;
|
||||
def CMP64ri8 : RIi8<0x83, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
|
||||
"cmp{q}\t{$src2, $src1|$src1, $src2}",
|
||||
[(X86cmp GR64:$src1, i64immSExt8:$src2)]>;
|
||||
} // Defs = [EFLAGS]
|
||||
|
||||
let Defs = [EFLAGS] in {
|
||||
let isCommutable = 1 in
|
||||
def NEW_TEST64rr : RI<0x85, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
|
||||
"test{q}\t{$src2, $src1|$src1, $src2}",
|
||||
[(X86cmp_new (and GR64:$src1, GR64:$src2), 0),
|
||||
(implicit EFLAGS)]>;
|
||||
def NEW_TEST64rm : RI<0x85, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
|
||||
"test{q}\t{$src2, $src1|$src1, $src2}",
|
||||
[(X86cmp_new (and GR64:$src1, (loadi64 addr:$src2)), 0),
|
||||
(implicit EFLAGS)]>;
|
||||
def NEW_TEST64ri32 : RIi32<0xF7, MRM0r, (outs),
|
||||
(ins GR64:$src1, i64i32imm:$src2),
|
||||
"test{q}\t{$src2, $src1|$src1, $src2}",
|
||||
[(X86cmp_new (and GR64:$src1, i64immSExt32:$src2), 0),
|
||||
(implicit EFLAGS)]>;
|
||||
def NEW_TEST64mi32 : RIi32<0xF7, MRM0m, (outs),
|
||||
(ins i64mem:$src1, i64i32imm:$src2),
|
||||
"test{q}\t{$src2, $src1|$src1, $src2}",
|
||||
[(X86cmp_new (and (loadi64 addr:$src1), i64immSExt32:$src2), 0),
|
||||
(implicit EFLAGS)]>;
|
||||
|
||||
def NEW_CMP64rr : RI<0x39, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
|
||||
"cmp{q}\t{$src2, $src1|$src1, $src2}",
|
||||
[(X86cmp_new GR64:$src1, GR64:$src2),
|
||||
(implicit EFLAGS)]>;
|
||||
def NEW_CMP64mr : RI<0x39, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
|
||||
"cmp{q}\t{$src2, $src1|$src1, $src2}",
|
||||
[(X86cmp_new (loadi64 addr:$src1), GR64:$src2),
|
||||
(implicit EFLAGS)]>;
|
||||
def NEW_CMP64rm : RI<0x3B, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmp{q}\t{$src2, $src1|$src1, $src2}",
|
||||
[(X86cmp_new GR64:$src1, (loadi64 addr:$src2)),
|
||||
(implicit EFLAGS)]>;
|
||||
def NEW_CMP64ri32 : RIi32<0x81, MRM7r, (outs), (ins GR64:$src1, i64i32imm:$src2),
|
||||
"cmp{q}\t{$src2, $src1|$src1, $src2}",
|
||||
[(X86cmp_new GR64:$src1, i64immSExt32:$src2),
|
||||
[(X86cmp GR64:$src1, i64immSExt32:$src2),
|
||||
(implicit EFLAGS)]>;
|
||||
def NEW_CMP64mi32 : RIi32<0x81, MRM7m, (outs),
|
||||
def CMP64mi32 : RIi32<0x81, MRM7m, (outs),
|
||||
(ins i64mem:$src1, i64i32imm:$src2),
|
||||
"cmp{q}\t{$src2, $src1|$src1, $src2}",
|
||||
[(X86cmp_new (loadi64 addr:$src1), i64immSExt32:$src2),
|
||||
[(X86cmp (loadi64 addr:$src1), i64immSExt32:$src2),
|
||||
(implicit EFLAGS)]>;
|
||||
def NEW_CMP64mi8 : RIi8<0x83, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
|
||||
def CMP64mi8 : RIi8<0x83, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
|
||||
"cmp{q}\t{$src2, $src1|$src1, $src2}",
|
||||
[(X86cmp_new (loadi64 addr:$src1), i64immSExt8:$src2),
|
||||
[(X86cmp (loadi64 addr:$src1), i64immSExt8:$src2),
|
||||
(implicit EFLAGS)]>;
|
||||
def NEW_CMP64ri8 : RIi8<0x83, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
|
||||
def CMP64ri8 : RIi8<0x83, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
|
||||
"cmp{q}\t{$src2, $src1|$src1, $src2}",
|
||||
[(X86cmp_new GR64:$src1, i64immSExt8:$src2),
|
||||
[(X86cmp GR64:$src1, i64immSExt8:$src2),
|
||||
(implicit EFLAGS)]>;
|
||||
} // Defs = [EFLAGS]
|
||||
|
||||
@ -815,282 +777,141 @@ def CMOVB64rr : RI<0x42, MRMSrcReg, // if <u, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovb\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
||||
X86_COND_B))]>, TB;
|
||||
X86_COND_B, EFLAGS))]>, TB;
|
||||
def CMOVB64rm : RI<0x42, MRMSrcMem, // if <u, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovb\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_B))]>, TB;
|
||||
X86_COND_B, EFLAGS))]>, TB;
|
||||
def CMOVAE64rr: RI<0x43, MRMSrcReg, // if >=u, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovae\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
||||
X86_COND_AE))]>, TB;
|
||||
X86_COND_AE, EFLAGS))]>, TB;
|
||||
def CMOVAE64rm: RI<0x43, MRMSrcMem, // if >=u, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovae\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_AE))]>, TB;
|
||||
X86_COND_AE, EFLAGS))]>, TB;
|
||||
def CMOVE64rr : RI<0x44, MRMSrcReg, // if ==, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmove\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
||||
X86_COND_E))]>, TB;
|
||||
X86_COND_E, EFLAGS))]>, TB;
|
||||
def CMOVE64rm : RI<0x44, MRMSrcMem, // if ==, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmove\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_E))]>, TB;
|
||||
X86_COND_E, EFLAGS))]>, TB;
|
||||
def CMOVNE64rr: RI<0x45, MRMSrcReg, // if !=, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovne\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
||||
X86_COND_NE))]>, TB;
|
||||
X86_COND_NE, EFLAGS))]>, TB;
|
||||
def CMOVNE64rm: RI<0x45, MRMSrcMem, // if !=, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovne\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_NE))]>, TB;
|
||||
X86_COND_NE, EFLAGS))]>, TB;
|
||||
def CMOVBE64rr: RI<0x46, MRMSrcReg, // if <=u, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovbe\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
||||
X86_COND_BE))]>, TB;
|
||||
X86_COND_BE, EFLAGS))]>, TB;
|
||||
def CMOVBE64rm: RI<0x46, MRMSrcMem, // if <=u, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovbe\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_BE))]>, TB;
|
||||
X86_COND_BE, EFLAGS))]>, TB;
|
||||
def CMOVA64rr : RI<0x47, MRMSrcReg, // if >u, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmova\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
||||
X86_COND_A))]>, TB;
|
||||
X86_COND_A, EFLAGS))]>, TB;
|
||||
def CMOVA64rm : RI<0x47, MRMSrcMem, // if >u, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmova\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_A))]>, TB;
|
||||
X86_COND_A, EFLAGS))]>, TB;
|
||||
def CMOVL64rr : RI<0x4C, MRMSrcReg, // if <s, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovl\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
||||
X86_COND_L))]>, TB;
|
||||
X86_COND_L, EFLAGS))]>, TB;
|
||||
def CMOVL64rm : RI<0x4C, MRMSrcMem, // if <s, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovl\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_L))]>, TB;
|
||||
X86_COND_L, EFLAGS))]>, TB;
|
||||
def CMOVGE64rr: RI<0x4D, MRMSrcReg, // if >=s, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovge\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
||||
X86_COND_GE))]>, TB;
|
||||
X86_COND_GE, EFLAGS))]>, TB;
|
||||
def CMOVGE64rm: RI<0x4D, MRMSrcMem, // if >=s, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovge\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_GE))]>, TB;
|
||||
X86_COND_GE, EFLAGS))]>, TB;
|
||||
def CMOVLE64rr: RI<0x4E, MRMSrcReg, // if <=s, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovle\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
||||
X86_COND_LE))]>, TB;
|
||||
X86_COND_LE, EFLAGS))]>, TB;
|
||||
def CMOVLE64rm: RI<0x4E, MRMSrcMem, // if <=s, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovle\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_LE))]>, TB;
|
||||
X86_COND_LE, EFLAGS))]>, TB;
|
||||
def CMOVG64rr : RI<0x4F, MRMSrcReg, // if >s, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovg\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
||||
X86_COND_G))]>, TB;
|
||||
X86_COND_G, EFLAGS))]>, TB;
|
||||
def CMOVG64rm : RI<0x4F, MRMSrcMem, // if >s, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovg\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_G))]>, TB;
|
||||
X86_COND_G, EFLAGS))]>, TB;
|
||||
def CMOVS64rr : RI<0x48, MRMSrcReg, // if signed, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovs\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
||||
X86_COND_S))]>, TB;
|
||||
X86_COND_S, EFLAGS))]>, TB;
|
||||
def CMOVS64rm : RI<0x48, MRMSrcMem, // if signed, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovs\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_S))]>, TB;
|
||||
X86_COND_S, EFLAGS))]>, TB;
|
||||
def CMOVNS64rr: RI<0x49, MRMSrcReg, // if !signed, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovns\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
||||
X86_COND_NS))]>, TB;
|
||||
X86_COND_NS, EFLAGS))]>, TB;
|
||||
def CMOVNS64rm: RI<0x49, MRMSrcMem, // if !signed, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovns\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_NS))]>, TB;
|
||||
X86_COND_NS, EFLAGS))]>, TB;
|
||||
def CMOVP64rr : RI<0x4A, MRMSrcReg, // if parity, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovp\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
||||
X86_COND_P))]>, TB;
|
||||
X86_COND_P, EFLAGS))]>, TB;
|
||||
def CMOVP64rm : RI<0x4A, MRMSrcMem, // if parity, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovp\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_P))]>, TB;
|
||||
X86_COND_P, EFLAGS))]>, TB;
|
||||
def CMOVNP64rr : RI<0x4B, MRMSrcReg, // if !parity, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovnp\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
||||
X86_COND_NP))]>, TB;
|
||||
X86_COND_NP, EFLAGS))]>, TB;
|
||||
def CMOVNP64rm : RI<0x4B, MRMSrcMem, // if !parity, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovnp\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_NP))]>, TB;
|
||||
|
||||
def NEW_CMOVB64rr : RI<0x42, MRMSrcReg, // if <u, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovb\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov_new GR64:$src1, GR64:$src2,
|
||||
X86_COND_B, EFLAGS))]>, TB;
|
||||
def NEW_CMOVB64rm : RI<0x42, MRMSrcMem, // if <u, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovb\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov_new GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_B, EFLAGS))]>, TB;
|
||||
def NEW_CMOVAE64rr: RI<0x43, MRMSrcReg, // if >=u, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovae\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov_new GR64:$src1, GR64:$src2,
|
||||
X86_COND_AE, EFLAGS))]>, TB;
|
||||
def NEW_CMOVAE64rm: RI<0x43, MRMSrcMem, // if >=u, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovae\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov_new GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_AE, EFLAGS))]>, TB;
|
||||
def NEW_CMOVE64rr : RI<0x44, MRMSrcReg, // if ==, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmove\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov_new GR64:$src1, GR64:$src2,
|
||||
X86_COND_E, EFLAGS))]>, TB;
|
||||
def NEW_CMOVE64rm : RI<0x44, MRMSrcMem, // if ==, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmove\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov_new GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_E, EFLAGS))]>, TB;
|
||||
def NEW_CMOVNE64rr: RI<0x45, MRMSrcReg, // if !=, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovne\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov_new GR64:$src1, GR64:$src2,
|
||||
X86_COND_NE, EFLAGS))]>, TB;
|
||||
def NEW_CMOVNE64rm: RI<0x45, MRMSrcMem, // if !=, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovne\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov_new GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_NE, EFLAGS))]>, TB;
|
||||
def NEW_CMOVBE64rr: RI<0x46, MRMSrcReg, // if <=u, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovbe\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov_new GR64:$src1, GR64:$src2,
|
||||
X86_COND_BE, EFLAGS))]>, TB;
|
||||
def NEW_CMOVBE64rm: RI<0x46, MRMSrcMem, // if <=u, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovbe\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov_new GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_BE, EFLAGS))]>, TB;
|
||||
def NEW_CMOVA64rr : RI<0x47, MRMSrcReg, // if >u, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmova\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov_new GR64:$src1, GR64:$src2,
|
||||
X86_COND_A, EFLAGS))]>, TB;
|
||||
def NEW_CMOVA64rm : RI<0x47, MRMSrcMem, // if >u, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmova\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov_new GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_A, EFLAGS))]>, TB;
|
||||
def NEW_CMOVL64rr : RI<0x4C, MRMSrcReg, // if <s, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovl\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov_new GR64:$src1, GR64:$src2,
|
||||
X86_COND_L, EFLAGS))]>, TB;
|
||||
def NEW_CMOVL64rm : RI<0x4C, MRMSrcMem, // if <s, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovl\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov_new GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_L, EFLAGS))]>, TB;
|
||||
def NEW_CMOVGE64rr: RI<0x4D, MRMSrcReg, // if >=s, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovge\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov_new GR64:$src1, GR64:$src2,
|
||||
X86_COND_GE, EFLAGS))]>, TB;
|
||||
def NEW_CMOVGE64rm: RI<0x4D, MRMSrcMem, // if >=s, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovge\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov_new GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_GE, EFLAGS))]>, TB;
|
||||
def NEW_CMOVLE64rr: RI<0x4E, MRMSrcReg, // if <=s, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovle\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov_new GR64:$src1, GR64:$src2,
|
||||
X86_COND_LE, EFLAGS))]>, TB;
|
||||
def NEW_CMOVLE64rm: RI<0x4E, MRMSrcMem, // if <=s, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovle\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov_new GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_LE, EFLAGS))]>, TB;
|
||||
def NEW_CMOVG64rr : RI<0x4F, MRMSrcReg, // if >s, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovg\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov_new GR64:$src1, GR64:$src2,
|
||||
X86_COND_G, EFLAGS))]>, TB;
|
||||
def NEW_CMOVG64rm : RI<0x4F, MRMSrcMem, // if >s, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovg\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov_new GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_G, EFLAGS))]>, TB;
|
||||
def NEW_CMOVS64rr : RI<0x48, MRMSrcReg, // if signed, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovs\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov_new GR64:$src1, GR64:$src2,
|
||||
X86_COND_S, EFLAGS))]>, TB;
|
||||
def NEW_CMOVS64rm : RI<0x48, MRMSrcMem, // if signed, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovs\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov_new GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_S, EFLAGS))]>, TB;
|
||||
def NEW_CMOVNS64rr: RI<0x49, MRMSrcReg, // if !signed, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovns\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov_new GR64:$src1, GR64:$src2,
|
||||
X86_COND_NS, EFLAGS))]>, TB;
|
||||
def NEW_CMOVNS64rm: RI<0x49, MRMSrcMem, // if !signed, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovns\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov_new GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_NS, EFLAGS))]>, TB;
|
||||
def NEW_CMOVP64rr : RI<0x4A, MRMSrcReg, // if parity, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovp\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov_new GR64:$src1, GR64:$src2,
|
||||
X86_COND_P, EFLAGS))]>, TB;
|
||||
def NEW_CMOVP64rm : RI<0x4A, MRMSrcMem, // if parity, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovp\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov_new GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_P, EFLAGS))]>, TB;
|
||||
def NEW_CMOVNP64rr : RI<0x4B, MRMSrcReg, // if !parity, GR64 = GR64
|
||||
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
"cmovnp\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov_new GR64:$src1, GR64:$src2,
|
||||
X86_COND_NP, EFLAGS))]>, TB;
|
||||
def NEW_CMOVNP64rm : RI<0x4B, MRMSrcMem, // if !parity, GR64 = [mem64]
|
||||
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
"cmovnp\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (X86cmov_new GR64:$src1, (loadi64 addr:$src2),
|
||||
X86_COND_NP, EFLAGS))]>, TB;
|
||||
} // isTwoAddress
|
||||
|
||||
@ -1279,12 +1100,9 @@ def : Pat<(X86tailcall GR64:$dst),
|
||||
// Comparisons.
|
||||
|
||||
// TEST R,R is smaller than CMP R,0
|
||||
def : Pat<(X86cmp GR64:$src1, 0),
|
||||
def : Pat<(parallel (X86cmp GR64:$src1, 0), (implicit EFLAGS)),
|
||||
(TEST64rr GR64:$src1, GR64:$src1)>;
|
||||
|
||||
def : Pat<(parallel (X86cmp_new GR64:$src1, 0), (implicit EFLAGS)),
|
||||
(NEW_TEST64rr GR64:$src1, GR64:$src1)>;
|
||||
|
||||
// {s|z}extload bool -> {s|z}extload byte
|
||||
def : Pat<(sextloadi64i1 addr:$src), (MOVSX64rm8 addr:$src)>;
|
||||
def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
|
||||
|
||||
@ -716,34 +716,6 @@ X86RegisterInfo::foldMemoryOperand(MachineInstr *MI, unsigned i,
|
||||
{ X86::MUL32r, X86::MUL32m },
|
||||
{ X86::MUL64r, X86::MUL64m },
|
||||
{ X86::MUL8r, X86::MUL8m },
|
||||
|
||||
// TEMPORARY
|
||||
{ X86::NEW_CMP16ri, X86::NEW_CMP16mi },
|
||||
{ X86::NEW_CMP16ri8,X86::NEW_CMP16mi8 },
|
||||
{ X86::NEW_CMP32ri, X86::NEW_CMP32mi },
|
||||
{ X86::NEW_CMP32ri8,X86::NEW_CMP32mi8 },
|
||||
{ X86::NEW_CMP64ri32,X86::NEW_CMP64mi32 },
|
||||
{ X86::NEW_CMP64ri8,X86::NEW_CMP64mi8 },
|
||||
{ X86::NEW_CMP8ri, X86::NEW_CMP8mi },
|
||||
{ X86::NEW_SETAEr, X86::NEW_SETAEm },
|
||||
{ X86::NEW_SETAr, X86::NEW_SETAm },
|
||||
{ X86::NEW_SETBEr, X86::NEW_SETBEm },
|
||||
{ X86::NEW_SETBr, X86::NEW_SETBm },
|
||||
{ X86::NEW_SETEr, X86::NEW_SETEm },
|
||||
{ X86::NEW_SETGEr, X86::NEW_SETGEm },
|
||||
{ X86::NEW_SETGr, X86::NEW_SETGm },
|
||||
{ X86::NEW_SETLEr, X86::NEW_SETLEm },
|
||||
{ X86::NEW_SETLr, X86::NEW_SETLm },
|
||||
{ X86::NEW_SETNEr, X86::NEW_SETNEm },
|
||||
{ X86::NEW_SETNPr, X86::NEW_SETNPm },
|
||||
{ X86::NEW_SETNSr, X86::NEW_SETNSm },
|
||||
{ X86::NEW_SETPr, X86::NEW_SETPm },
|
||||
{ X86::NEW_SETSr, X86::NEW_SETSm },
|
||||
{ X86::NEW_TEST16ri,X86::NEW_TEST16mi },
|
||||
{ X86::NEW_TEST32ri,X86::NEW_TEST32mi },
|
||||
{ X86::NEW_TEST64ri32, X86::NEW_TEST64mi32 },
|
||||
{ X86::NEW_TEST8ri, X86::NEW_TEST8mi },
|
||||
|
||||
{ X86::SETAEr, X86::SETAEm },
|
||||
{ X86::SETAr, X86::SETAm },
|
||||
{ X86::SETBEr, X86::SETBEm },
|
||||
@ -854,23 +826,6 @@ X86RegisterInfo::foldMemoryOperand(MachineInstr *MI, unsigned i,
|
||||
{ X86::MOVZX32rr8, X86::MOVZX32rm8 },
|
||||
{ X86::MOVZX64rr16, X86::MOVZX64rm16 },
|
||||
{ X86::MOVZX64rr8, X86::MOVZX64rm8 },
|
||||
|
||||
// TEMPORARY
|
||||
{ X86::NEW_CMP16rr, X86::NEW_CMP16rm },
|
||||
{ X86::NEW_CMP32rr, X86::NEW_CMP32rm },
|
||||
{ X86::NEW_CMP64rr, X86::NEW_CMP64rm },
|
||||
{ X86::NEW_CMP8rr, X86::NEW_CMP8rm },
|
||||
{ X86::NEW_Int_COMISDrr, X86::NEW_Int_COMISDrm },
|
||||
{ X86::NEW_Int_COMISSrr, X86::NEW_Int_COMISSrm },
|
||||
{ X86::NEW_Int_UCOMISDrr, X86::NEW_Int_UCOMISDrm },
|
||||
{ X86::NEW_Int_UCOMISSrr, X86::NEW_Int_UCOMISSrm },
|
||||
{ X86::NEW_TEST16rr, X86::NEW_TEST16rm },
|
||||
{ X86::NEW_TEST32rr, X86::NEW_TEST32rm },
|
||||
{ X86::NEW_TEST64rr, X86::NEW_TEST64rm },
|
||||
{ X86::NEW_TEST8rr, X86::NEW_TEST8rm },
|
||||
{ X86::NEW_UCOMISDrr, X86::NEW_UCOMISDrm },
|
||||
{ X86::NEW_UCOMISSrr, X86::NEW_UCOMISSrm },
|
||||
|
||||
{ X86::PSHUFDri, X86::PSHUFDmi },
|
||||
{ X86::PSHUFHWri, X86::PSHUFHWmi },
|
||||
{ X86::PSHUFLWri, X86::PSHUFLWmi },
|
||||
@ -1004,51 +959,6 @@ X86RegisterInfo::foldMemoryOperand(MachineInstr *MI, unsigned i,
|
||||
{ X86::MULPSrr, X86::MULPSrm },
|
||||
{ X86::MULSDrr, X86::MULSDrm },
|
||||
{ X86::MULSSrr, X86::MULSSrm },
|
||||
|
||||
// TEMPORARY
|
||||
{ X86::NEW_CMOVA16rr, X86::NEW_CMOVA16rm },
|
||||
{ X86::NEW_CMOVA32rr, X86::NEW_CMOVA32rm },
|
||||
{ X86::NEW_CMOVA64rr, X86::NEW_CMOVA64rm },
|
||||
{ X86::NEW_CMOVAE16rr, X86::NEW_CMOVAE16rm },
|
||||
{ X86::NEW_CMOVAE32rr, X86::NEW_CMOVAE32rm },
|
||||
{ X86::NEW_CMOVAE64rr, X86::NEW_CMOVAE64rm },
|
||||
{ X86::NEW_CMOVB16rr, X86::NEW_CMOVB16rm },
|
||||
{ X86::NEW_CMOVB32rr, X86::NEW_CMOVB32rm },
|
||||
{ X86::NEW_CMOVB64rr, X86::NEW_CMOVB64rm },
|
||||
{ X86::NEW_CMOVBE16rr, X86::NEW_CMOVBE16rm },
|
||||
{ X86::NEW_CMOVBE32rr, X86::NEW_CMOVBE32rm },
|
||||
{ X86::NEW_CMOVBE64rr, X86::NEW_CMOVBE64rm },
|
||||
{ X86::NEW_CMOVE16rr, X86::NEW_CMOVE16rm },
|
||||
{ X86::NEW_CMOVE32rr, X86::NEW_CMOVE32rm },
|
||||
{ X86::NEW_CMOVE64rr, X86::NEW_CMOVE64rm },
|
||||
{ X86::NEW_CMOVG16rr, X86::NEW_CMOVG16rm },
|
||||
{ X86::NEW_CMOVG32rr, X86::NEW_CMOVG32rm },
|
||||
{ X86::NEW_CMOVG64rr, X86::NEW_CMOVG64rm },
|
||||
{ X86::NEW_CMOVGE16rr, X86::NEW_CMOVGE16rm },
|
||||
{ X86::NEW_CMOVGE32rr, X86::NEW_CMOVGE32rm },
|
||||
{ X86::NEW_CMOVGE64rr, X86::NEW_CMOVGE64rm },
|
||||
{ X86::NEW_CMOVL16rr, X86::NEW_CMOVL16rm },
|
||||
{ X86::NEW_CMOVL32rr, X86::NEW_CMOVL32rm },
|
||||
{ X86::NEW_CMOVL64rr, X86::NEW_CMOVL64rm },
|
||||
{ X86::NEW_CMOVLE16rr, X86::NEW_CMOVLE16rm },
|
||||
{ X86::NEW_CMOVLE32rr, X86::NEW_CMOVLE32rm },
|
||||
{ X86::NEW_CMOVLE64rr, X86::NEW_CMOVLE64rm },
|
||||
{ X86::NEW_CMOVNE16rr, X86::NEW_CMOVNE16rm },
|
||||
{ X86::NEW_CMOVNE32rr, X86::NEW_CMOVNE32rm },
|
||||
{ X86::NEW_CMOVNE64rr, X86::NEW_CMOVNE64rm },
|
||||
{ X86::NEW_CMOVNP16rr, X86::NEW_CMOVNP16rm },
|
||||
{ X86::NEW_CMOVNP32rr, X86::NEW_CMOVNP32rm },
|
||||
{ X86::NEW_CMOVNP64rr, X86::NEW_CMOVNP64rm },
|
||||
{ X86::NEW_CMOVNS16rr, X86::NEW_CMOVNS16rm },
|
||||
{ X86::NEW_CMOVNS32rr, X86::NEW_CMOVNS32rm },
|
||||
{ X86::NEW_CMOVNS64rr, X86::NEW_CMOVNS64rm },
|
||||
{ X86::NEW_CMOVP16rr, X86::NEW_CMOVP16rm },
|
||||
{ X86::NEW_CMOVP32rr, X86::NEW_CMOVP32rm },
|
||||
{ X86::NEW_CMOVP64rr, X86::NEW_CMOVP64rm },
|
||||
{ X86::NEW_CMOVS16rr, X86::NEW_CMOVS16rm },
|
||||
{ X86::NEW_CMOVS32rr, X86::NEW_CMOVS32rm },
|
||||
{ X86::NEW_CMOVS64rr, X86::NEW_CMOVS64rm },
|
||||
|
||||
{ X86::OR16rr, X86::OR16rm },
|
||||
{ X86::OR32rr, X86::OR32rm },
|
||||
{ X86::OR64rr, X86::OR64rm },
|
||||
|
||||
Loading…
Reference in New Issue
Block a user