6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-07-29 10:25:12 +00:00
Code Issues Projects Releases Wiki Activity

[mips][microMIPS] Implement LWSP and SWSP instructions

Browse Source 
Differential Revision: http://reviews.llvm.org/D6416


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224771 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jozef Kolek
2014-12-23 16:16:33 +00:00
parent 127090dd75
commit e5fa612e9e
10 changed files with 126 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

21
lib/Target/Mips/Disassembler/MipsDisassembler.cpp
View File

@@ -265,6 +265,11 @@ static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
unsigned Insn,
uint64_t Address,
@@ -1197,6 +1202,22 @@ static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
return MCDisassembler::Success;
}
static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder) {
unsigned Offset = Insn & 0x1F;
unsigned Reg = fieldFromInstruction(Insn, 5, 5);
Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
Inst.addOperand(MCOperand::CreateReg(Reg));
Inst.addOperand(MCOperand::CreateReg(Mips::SP));
Inst.addOperand(MCOperand::CreateImm(Offset << 2));
return MCDisassembler::Success;
}
static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
unsigned Insn,
uint64_t Address,