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Add some more sign propagation cases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28154 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1068,16 +1068,6 @@ unsigned TargetLowering::ComputeNumSignBits(SDOperand Op, unsigned Depth) const{
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return Tmp - C->getValue();
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}
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break;
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case ISD::ADD:
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case ISD::SUB:
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// Add and sub can have at most one carry bit. Thus we know that the output
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// is, at worst, one more bit than the inputs.
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Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
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if (Tmp == 1) return 1; // Early out.
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Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1);
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if (Tmp2 == 1) return 1;
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return std::min(Tmp, Tmp2)-1;
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case ISD::AND:
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case ISD::OR:
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case ISD::XOR: // NOT is handled here.
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@ -1098,6 +1088,83 @@ unsigned TargetLowering::ComputeNumSignBits(SDOperand Op, unsigned Depth) const{
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if (getSetCCResultContents() == ZeroOrNegativeOneSetCCResult)
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return VTBits;
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break;
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case ISD::ROTL:
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case ISD::ROTR:
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
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unsigned RotAmt = C->getValue() & (VTBits-1);
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// Handle rotate right by N like a rotate left by 32-N.
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if (Op.getOpcode() == ISD::ROTR)
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RotAmt = (VTBits-RotAmt) & (VTBits-1);
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// If we aren't rotating out all of the known-in sign bits, return the
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// number that are left. This handles rotl(sext(x), 1) for example.
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Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
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if (Tmp > RotAmt+1) return Tmp-RotAmt;
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}
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break;
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case ISD::ADD:
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// Add can have at most one carry bit. Thus we know that the output
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// is, at worst, one more bit than the inputs.
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Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
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if (Tmp == 1) return 1; // Early out.
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// Special case decrementing a value (ADD X, -1):
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if (ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(Op.getOperand(0)))
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if (CRHS->isAllOnesValue()) {
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uint64_t KnownZero, KnownOne;
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uint64_t Mask = MVT::getIntVTBitMask(VT);
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ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
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// If the input is known to be 0 or 1, the output is 0/-1, which is all
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// sign bits set.
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if ((KnownZero|1) == Mask)
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return VTBits;
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// If we are subtracting one from a positive number, there is no carry
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// out of the result.
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if (KnownZero & MVT::getIntVTSignBit(VT))
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return Tmp;
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}
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Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1);
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if (Tmp2 == 1) return 1;
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return std::min(Tmp, Tmp2)-1;
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break;
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case ISD::SUB:
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Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1);
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if (Tmp2 == 1) return 1;
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// Handle NEG.
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if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0)))
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if (CLHS->getValue() == 0) {
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uint64_t KnownZero, KnownOne;
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uint64_t Mask = MVT::getIntVTBitMask(VT);
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ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
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// If the input is known to be 0 or 1, the output is 0/-1, which is all
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// sign bits set.
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if ((KnownZero|1) == Mask)
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return VTBits;
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// If the input is known to be positive (the sign bit is known clear),
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// the output of the NEG has the same number of sign bits as the input.
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if (KnownZero & MVT::getIntVTSignBit(VT))
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return Tmp2;
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// Otherwise, we treat this like a SUB.
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}
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// Sub can have at most one carry bit. Thus we know that the output
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// is, at worst, one more bit than the inputs.
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Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
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if (Tmp == 1) return 1; // Early out.
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return std::min(Tmp, Tmp2)-1;
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break;
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case ISD::TRUNCATE:
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// FIXME: it's tricky to do anything useful for this, but it is an important
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// case for targets like X86.
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break;
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}
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// Allow the target to implement this method for its nodes.
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