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Handle AddrMode6 (for NEON load/stores) in Thumb2's rewriteT2FrameIndex.

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Radar 7614112.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95456 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson
2010-02-06 00:24:38 +00:00
parent d450e5b886
commit e6373eb826
2 changed files with 12 additions and 13 deletions
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21
lib/Target/ARM/Thumb2InstrInfo.cpp
View File

@ -382,8 +382,8 @@ bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal); MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
} else { } else {
// AddrMode4 cannot handle any offset. // AddrMode4 and AddrMode6 cannot handle any offset.
if (AddrMode == ARMII::AddrMode4) if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
return false; return false;
// AddrModeT2_so cannot handle any offset. If there is no offset // AddrModeT2_so cannot handle any offset. If there is no offset
@ -418,15 +418,12 @@ bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
NewOpc = positiveOffsetOpcode(Opcode); NewOpc = positiveOffsetOpcode(Opcode);
NumBits = 12; NumBits = 12;
} }
} else { } else if (AddrMode == ARMII::AddrMode5) {
// VFP and NEON address modes. // VFP address mode.
int InstrOffs = 0; const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1);
if (AddrMode == ARMII::AddrMode5) { int InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1); if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm()); InstrOffs *= -1;
if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
InstrOffs *= -1;
}
NumBits = 8; NumBits = 8;
Scale = 4; Scale = 4;
Offset += InstrOffs * 4; Offset += InstrOffs * 4;
@ -435,6 +432,8 @@ bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
Offset = -Offset; Offset = -Offset;
isSub = true; isSub = true;
} }
} else {
llvm_unreachable("Unsupported addressing mode!");
} }
if (NewOpc != Opcode) if (NewOpc != Opcode)

4
test/CodeGen/Thumb2/thumb2-spill-q.ll
View File

@ -12,8 +12,8 @@ declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*) nounwind readonly
define arm_apcscc void @aaa(%quuz* %this, i8* %block) { define arm_apcscc void @aaa(%quuz* %this, i8* %block) {
; CHECK: aaa: ; CHECK: aaa:
; CHECK: bic r4, r4, #15 ; CHECK: bic r4, r4, #15
; CHECK: vst1.64 {{.*}}sp, :128 ; CHECK: vst1.64 {{.*}}[r{{.*}}, :128]
; CHECK: vld1.64 {{.*}}sp, :128 ; CHECK: vld1.64 {{.*}}[r{{.*}}, :128]
entry: entry:
%0 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef) nounwind ; <<4 x float>> [#uses=1] %0 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef) nounwind ; <<4 x float>> [#uses=1]
store float 6.300000e+01, float* undef, align 4 store float 6.300000e+01, float* undef, align 4