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[C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. PowerPC edition

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207504 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2014-04-29 07:57:37 +00:00
parent c279ae979e
commit e651935ab8
24 changed files with 306 additions and 301 deletions
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37
lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
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@ -230,7 +230,7 @@ class PPCAsmParser : public MCTargetAsmParser {
bool MatchRegisterName(const AsmToken &Tok, bool MatchRegisterName(const AsmToken &Tok,
unsigned &RegNo, int64_t &IntVal); unsigned &RegNo, int64_t &IntVal);
virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc); bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
const MCExpr *ExtractModifierFromExpr(const MCExpr *E, const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
PPCMCExpr::VariantKind &Variant); PPCMCExpr::VariantKind &Variant);
@ -248,7 +248,7 @@ class PPCAsmParser : public MCTargetAsmParser {
bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
SmallVectorImpl<MCParsedAsmOperand*> &Operands, SmallVectorImpl<MCParsedAsmOperand*> &Operands,
MCStreamer &Out, unsigned &ErrorInfo, MCStreamer &Out, unsigned &ErrorInfo,
bool MatchingInlineAsm); bool MatchingInlineAsm) override;
void ProcessInstruction(MCInst &Inst, void ProcessInstruction(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &Ops); const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
@ -276,17 +276,18 @@ public:
setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
} }
virtual bool ParseInstruction(ParseInstructionInfo &Info, bool ParseInstruction(ParseInstructionInfo &Info,
StringRef Name, SMLoc NameLoc, StringRef Name, SMLoc NameLoc,
SmallVectorImpl<MCParsedAsmOperand*> &Operands); SmallVectorImpl<MCParsedAsmOperand*> &Operands) override;
virtual bool ParseDirective(AsmToken DirectiveID); bool ParseDirective(AsmToken DirectiveID) override;
unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, unsigned Kind); unsigned validateTargetOperandClass(MCParsedAsmOperand *Op,
unsigned Kind) override;
virtual const MCExpr *applyModifierToExpr(const MCExpr *E, const MCExpr *applyModifierToExpr(const MCExpr *E,
MCSymbolRefExpr::VariantKind, MCSymbolRefExpr::VariantKind,
MCContext &Ctx); MCContext &Ctx) override;
}; };
/// PPCOperand - Instances of this class represent a parsed PowerPC machine /// PPCOperand - Instances of this class represent a parsed PowerPC machine
@ -351,10 +352,10 @@ public:
} }
/// getStartLoc - Get the location of the first token of this operand. /// getStartLoc - Get the location of the first token of this operand.
SMLoc getStartLoc() const { return StartLoc; } SMLoc getStartLoc() const override { return StartLoc; }
/// getEndLoc - Get the location of the last token of this operand. /// getEndLoc - Get the location of the last token of this operand.
SMLoc getEndLoc() const { return EndLoc; } SMLoc getEndLoc() const override { return EndLoc; }
/// isPPC64 - True if this operand is for an instruction in 64-bit mode. /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
bool isPPC64() const { return IsPPC64; } bool isPPC64() const { return IsPPC64; }
@ -379,7 +380,7 @@ public:
return TLSReg.Sym; return TLSReg.Sym;
} }
unsigned getReg() const { unsigned getReg() const override {
assert(isRegNumber() && "Invalid access!"); assert(isRegNumber() && "Invalid access!");
return (unsigned) Imm.Val; return (unsigned) Imm.Val;
} }
@ -404,8 +405,8 @@ public:
return 7 - countTrailingZeros<uint64_t>(Imm.Val); return 7 - countTrailingZeros<uint64_t>(Imm.Val);
} }
bool isToken() const { return Kind == Token; } bool isToken() const override { return Kind == Token; }
bool isImm() const { return Kind == Immediate || Kind == Expression; } bool isImm() const override { return Kind == Immediate || Kind == Expression; }
bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); } bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); }
bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); } bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); } bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
@ -438,8 +439,8 @@ public:
&& isUInt<5>(getImm())); } && isUInt<5>(getImm())); }
bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) && bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
isPowerOf2_32(getImm()); } isPowerOf2_32(getImm()); }
bool isMem() const { return false; } bool isMem() const override { return false; }
bool isReg() const { return false; } bool isReg() const override { return false; }
void addRegOperands(MCInst &Inst, unsigned N) const { void addRegOperands(MCInst &Inst, unsigned N) const {
llvm_unreachable("addRegOperands"); llvm_unreachable("addRegOperands");
@ -545,7 +546,7 @@ public:
return StringRef(Tok.Data, Tok.Length); return StringRef(Tok.Data, Tok.Length);
} }
virtual void print(raw_ostream &OS) const; void print(raw_ostream &OS) const override;
static PPCOperand *CreateToken(StringRef Str, SMLoc S, bool IsPPC64) { static PPCOperand *CreateToken(StringRef Str, SMLoc S, bool IsPPC64) {
PPCOperand *Op = new PPCOperand(Token); PPCOperand *Op = new PPCOperand(Token);

4
lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h
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@ -31,8 +31,8 @@ public:
return IsDarwin; return IsDarwin;
} }
virtual void printRegName(raw_ostream &OS, unsigned RegNo) const; void printRegName(raw_ostream &OS, unsigned RegNo) const override;
virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot); void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override;
// Autogenerated by tblgen. // Autogenerated by tblgen.
void printInstruction(const MCInst *MI, raw_ostream &O); void printInstruction(const MCInst *MI, raw_ostream &O);

20
lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
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@ -77,9 +77,11 @@ public:
PPCAsmBackend(const Target &T, bool isLittle) : MCAsmBackend(), TheTarget(T), PPCAsmBackend(const Target &T, bool isLittle) : MCAsmBackend(), TheTarget(T),
IsLittleEndian(isLittle) {} IsLittleEndian(isLittle) {}
unsigned getNumFixupKinds() const { return PPC::NumTargetFixupKinds; } unsigned getNumFixupKinds() const override {
return PPC::NumTargetFixupKinds;
}
const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const { const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
const static MCFixupKindInfo InfosBE[PPC::NumTargetFixupKinds] = { const static MCFixupKindInfo InfosBE[PPC::NumTargetFixupKinds] = {
// name offset bits flags // name offset bits flags
{ "fixup_ppc_br24", 6, 24, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_ppc_br24", 6, 24, MCFixupKindInfo::FKF_IsPCRel },
@ -110,7 +112,7 @@ public:
} }
void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
uint64_t Value, bool IsPCRel) const { uint64_t Value, bool IsPCRel) const override {
Value = adjustFixupValue(Fixup.getKind(), Value); Value = adjustFixupValue(Fixup.getKind(), Value);
if (!Value) return; // Doesn't change encoding. if (!Value) return; // Doesn't change encoding.
@ -126,7 +128,7 @@ public:
} }
} }
bool mayNeedRelaxation(const MCInst &Inst) const { bool mayNeedRelaxation(const MCInst &Inst) const override {
// FIXME. // FIXME.
return false; return false;
} }
@ -134,18 +136,18 @@ public:
bool fixupNeedsRelaxation(const MCFixup &Fixup, bool fixupNeedsRelaxation(const MCFixup &Fixup,
uint64_t Value, uint64_t Value,
const MCRelaxableFragment *DF, const MCRelaxableFragment *DF,
const MCAsmLayout &Layout) const { const MCAsmLayout &Layout) const override {
// FIXME. // FIXME.
llvm_unreachable("relaxInstruction() unimplemented"); llvm_unreachable("relaxInstruction() unimplemented");
} }
void relaxInstruction(const MCInst &Inst, MCInst &Res) const { void relaxInstruction(const MCInst &Inst, MCInst &Res) const override {
// FIXME. // FIXME.
llvm_unreachable("relaxInstruction() unimplemented"); llvm_unreachable("relaxInstruction() unimplemented");
} }
bool writeNopData(uint64_t Count, MCObjectWriter *OW) const { bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override {
uint64_t NumNops = Count / 4; uint64_t NumNops = Count / 4;
for (uint64_t i = 0; i != NumNops; ++i) for (uint64_t i = 0; i != NumNops; ++i)
OW->Write32(0x60000000); OW->Write32(0x60000000);
@ -180,7 +182,7 @@ namespace {
public: public:
DarwinPPCAsmBackend(const Target &T) : PPCAsmBackend(T, false) { } DarwinPPCAsmBackend(const Target &T) : PPCAsmBackend(T, false) { }
MCObjectWriter *createObjectWriter(raw_ostream &OS) const { MCObjectWriter *createObjectWriter(raw_ostream &OS) const override {
bool is64 = getPointerSize() == 8; bool is64 = getPointerSize() == 8;
return createPPCMachObjectWriter( return createPPCMachObjectWriter(
OS, OS,
@ -197,7 +199,7 @@ namespace {
PPCAsmBackend(T, IsLittleEndian), OSABI(OSABI) { } PPCAsmBackend(T, IsLittleEndian), OSABI(OSABI) { }
MCObjectWriter *createObjectWriter(raw_ostream &OS) const { MCObjectWriter *createObjectWriter(raw_ostream &OS) const override {
bool is64 = getPointerSize() == 8; bool is64 = getPointerSize() == 8;
return createPPCELFObjectWriter(OS, is64, isLittleEndian(), OSABI); return createPPCELFObjectWriter(OS, is64, isLittleEndian(), OSABI);
} }

4
lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h
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@ -21,13 +21,13 @@ namespace llvm {
class Triple; class Triple;
class PPCMCAsmInfoDarwin : public MCAsmInfoDarwin { class PPCMCAsmInfoDarwin : public MCAsmInfoDarwin {
virtual void anchor(); void anchor() override;
public: public:
explicit PPCMCAsmInfoDarwin(bool is64Bit, const Triple&); explicit PPCMCAsmInfoDarwin(bool is64Bit, const Triple&);
}; };
class PPCLinuxMCAsmInfo : public MCAsmInfoELF { class PPCLinuxMCAsmInfo : public MCAsmInfoELF {
virtual void anchor(); void anchor() override;
public: public:
explicit PPCLinuxMCAsmInfo(bool is64Bit, const Triple&); explicit PPCLinuxMCAsmInfo(bool is64Bit, const Triple&);
}; };

2
lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
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@ -89,7 +89,7 @@ public:
const MCSubtargetInfo &STI) const; const MCSubtargetInfo &STI) const;
void EncodeInstruction(const MCInst &MI, raw_ostream &OS, void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const { const MCSubtargetInfo &STI) const override {
// For fast-isel, a float COPY_TO_REGCLASS can survive this long. // For fast-isel, a float COPY_TO_REGCLASS can survive this long.
// It's just a nop to keep the register classes happy, so don't // It's just a nop to keep the register classes happy, so don't
// generate anything. // generate anything.

10
lib/Target/PowerPC/MCTargetDesc/PPCMCExpr.h
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@ -76,16 +76,16 @@ public:
/// @} /// @}
void PrintImpl(raw_ostream &OS) const; void PrintImpl(raw_ostream &OS) const override;
bool EvaluateAsRelocatableImpl(MCValue &Res, bool EvaluateAsRelocatableImpl(MCValue &Res,
const MCAsmLayout *Layout) const; const MCAsmLayout *Layout) const override;
void AddValueSymbols(MCAssembler *) const; void AddValueSymbols(MCAssembler *) const override;
const MCSection *FindAssociatedSection() const { const MCSection *FindAssociatedSection() const override {
return getSubExpr()->FindAssociatedSection(); return getSubExpr()->FindAssociatedSection();
} }
// There are no TLS PPCMCExprs at the moment. // There are no TLS PPCMCExprs at the moment.
void fixELFSymbolsInTLSFixups(MCAssembler &Asm) const {} void fixELFSymbolsInTLSFixups(MCAssembler &Asm) const override {}
static bool classof(const MCExpr *E) { static bool classof(const MCExpr *E) {
return E->getKind() == MCExpr::Target; return E->getKind() == MCExpr::Target;

12
lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
View File

@ -115,14 +115,14 @@ class PPCTargetAsmStreamer : public PPCTargetStreamer {
public: public:
PPCTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS) PPCTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS)
: PPCTargetStreamer(S), OS(OS) {} : PPCTargetStreamer(S), OS(OS) {}
virtual void emitTCEntry(const MCSymbol &S) { void emitTCEntry(const MCSymbol &S) override {
OS << "\t.tc "; OS << "\t.tc ";
OS << S.getName(); OS << S.getName();
OS << "[TC],"; OS << "[TC],";
OS << S.getName(); OS << S.getName();
OS << '\n'; OS << '\n';
} }
virtual void emitMachine(StringRef CPU) { void emitMachine(StringRef CPU) override {
OS << "\t.machine " << CPU << '\n'; OS << "\t.machine " << CPU << '\n';
} }
}; };
@ -130,11 +130,11 @@ public:
class PPCTargetELFStreamer : public PPCTargetStreamer { class PPCTargetELFStreamer : public PPCTargetStreamer {
public: public:
PPCTargetELFStreamer(MCStreamer &S) : PPCTargetStreamer(S) {} PPCTargetELFStreamer(MCStreamer &S) : PPCTargetStreamer(S) {}
virtual void emitTCEntry(const MCSymbol &S) { void emitTCEntry(const MCSymbol &S) override {
// Creates a R_PPC64_TOC relocation // Creates a R_PPC64_TOC relocation
Streamer.EmitSymbolValue(&S, 8); Streamer.EmitSymbolValue(&S, 8);
} }
virtual void emitMachine(StringRef CPU) { void emitMachine(StringRef CPU) override {
// FIXME: Is there anything to do in here or does this directive only // FIXME: Is there anything to do in here or does this directive only
// limit the parser? // limit the parser?
} }
@ -143,10 +143,10 @@ public:
class PPCTargetMachOStreamer : public PPCTargetStreamer { class PPCTargetMachOStreamer : public PPCTargetStreamer {
public: public:
PPCTargetMachOStreamer(MCStreamer &S) : PPCTargetStreamer(S) {} PPCTargetMachOStreamer(MCStreamer &S) : PPCTargetStreamer(S) {}
virtual void emitTCEntry(const MCSymbol &S) { void emitTCEntry(const MCSymbol &S) override {
llvm_unreachable("Unknown pseudo-op: .tc"); llvm_unreachable("Unknown pseudo-op: .tc");
} }
virtual void emitMachine(StringRef CPU) { void emitMachine(StringRef CPU) override {
// FIXME: We should update the CPUType, CPUSubType in the Object file if // FIXME: We should update the CPUType, CPUSubType in the Object file if
// the new values are different from the defaults. // the new values are different from the defaults.
} }

2
lib/Target/PowerPC/MCTargetDesc/PPCMachObjectWriter.cpp
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@ -44,7 +44,7 @@ public:
void RecordRelocation(MachObjectWriter *Writer, const MCAssembler &Asm, void RecordRelocation(MachObjectWriter *Writer, const MCAssembler &Asm,
const MCAsmLayout &Layout, const MCFragment *Fragment, const MCAsmLayout &Layout, const MCFragment *Fragment,
const MCFixup &Fixup, MCValue Target, const MCFixup &Fixup, MCValue Target,
uint64_t &FixedValue) { uint64_t &FixedValue) override {
if (Writer->is64Bit()) { if (Writer->is64Bit()) {
report_fatal_error("Relocation emission for MachO/PPC64 unimplemented."); report_fatal_error("Relocation emission for MachO/PPC64 unimplemented.");
} else } else

22
lib/Target/PowerPC/PPCAsmPrinter.cpp
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@ -71,22 +71,22 @@ namespace {
: AsmPrinter(TM, Streamer), : AsmPrinter(TM, Streamer),
Subtarget(TM.getSubtarget<PPCSubtarget>()), TOCLabelID(0) {} Subtarget(TM.getSubtarget<PPCSubtarget>()), TOCLabelID(0) {}
virtual const char *getPassName() const { const char *getPassName() const override {
return "PowerPC Assembly Printer"; return "PowerPC Assembly Printer";
} }
MCSymbol *lookUpOrCreateTOCEntry(MCSymbol *Sym); MCSymbol *lookUpOrCreateTOCEntry(MCSymbol *Sym);
virtual void EmitInstruction(const MachineInstr *MI); void EmitInstruction(const MachineInstr *MI) override;
void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O); void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O);
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
unsigned AsmVariant, const char *ExtraCode, unsigned AsmVariant, const char *ExtraCode,
raw_ostream &O); raw_ostream &O) override;
bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
unsigned AsmVariant, const char *ExtraCode, unsigned AsmVariant, const char *ExtraCode,
raw_ostream &O); raw_ostream &O) override;
}; };
/// PPCLinuxAsmPrinter - PowerPC assembly printer, customized for Linux /// PPCLinuxAsmPrinter - PowerPC assembly printer, customized for Linux
@ -95,15 +95,15 @@ namespace {
explicit PPCLinuxAsmPrinter(TargetMachine &TM, MCStreamer &Streamer) explicit PPCLinuxAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
: PPCAsmPrinter(TM, Streamer) {} : PPCAsmPrinter(TM, Streamer) {}
virtual const char *getPassName() const { const char *getPassName() const override {
return "Linux PPC Assembly Printer"; return "Linux PPC Assembly Printer";
} }
bool doFinalization(Module &M); bool doFinalization(Module &M) override;
virtual void EmitFunctionEntryLabel(); void EmitFunctionEntryLabel() override;
void EmitFunctionBodyEnd(); void EmitFunctionBodyEnd() override;
}; };
/// PPCDarwinAsmPrinter - PowerPC assembly printer, customized for Darwin/Mac /// PPCDarwinAsmPrinter - PowerPC assembly printer, customized for Darwin/Mac
@ -113,12 +113,12 @@ namespace {
explicit PPCDarwinAsmPrinter(TargetMachine &TM, MCStreamer &Streamer) explicit PPCDarwinAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
: PPCAsmPrinter(TM, Streamer) {} : PPCAsmPrinter(TM, Streamer) {}
virtual const char *getPassName() const { const char *getPassName() const override {
return "Darwin PPC Assembly Printer"; return "Darwin PPC Assembly Printer";
} }
bool doFinalization(Module &M); bool doFinalization(Module &M) override;
void EmitStartOfAsmFile(Module &M); void EmitStartOfAsmFile(Module &M) override;
void EmitFunctionStubs(const MachineModuleInfoMachO::SymbolListTy &Stubs); void EmitFunctionStubs(const MachineModuleInfoMachO::SymbolListTy &Stubs);
}; };

4
lib/Target/PowerPC/PPCBranchSelector.cpp
View File

@ -43,9 +43,9 @@ namespace {
/// BlockSizes - The sizes of the basic blocks in the function. /// BlockSizes - The sizes of the basic blocks in the function.
std::vector<unsigned> BlockSizes; std::vector<unsigned> BlockSizes;
virtual bool runOnMachineFunction(MachineFunction &Fn); bool runOnMachineFunction(MachineFunction &Fn) override;
virtual const char *getPassName() const { const char *getPassName() const override {
return "PowerPC Branch Selector"; return "PowerPC Branch Selector";
} }
}; };

8
lib/Target/PowerPC/PPCCTRLoops.cpp
View File

@ -91,9 +91,9 @@ namespace {
initializePPCCTRLoopsPass(*PassRegistry::getPassRegistry()); initializePPCCTRLoopsPass(*PassRegistry::getPassRegistry());
} }
virtual bool runOnFunction(Function &F); bool runOnFunction(Function &F) override;
virtual void getAnalysisUsage(AnalysisUsage &AU) const { void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired<LoopInfo>(); AU.addRequired<LoopInfo>();
AU.addPreserved<LoopInfo>(); AU.addPreserved<LoopInfo>();
AU.addRequired<DominatorTreeWrapperPass>(); AU.addRequired<DominatorTreeWrapperPass>();
@ -128,12 +128,12 @@ namespace {
initializePPCCTRLoopsVerifyPass(*PassRegistry::getPassRegistry()); initializePPCCTRLoopsVerifyPass(*PassRegistry::getPassRegistry());
} }
virtual void getAnalysisUsage(AnalysisUsage &AU) const { void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired<MachineDominatorTree>(); AU.addRequired<MachineDominatorTree>();
MachineFunctionPass::getAnalysisUsage(AU); MachineFunctionPass::getAnalysisUsage(AU);
} }
virtual bool runOnMachineFunction(MachineFunction &MF); bool runOnMachineFunction(MachineFunction &MF) override;
private: private:
MachineDominatorTree *MDT; MachineDominatorTree *MDT;

8
lib/Target/PowerPC/PPCCodeEmitter.cpp
View File

@ -32,7 +32,7 @@ namespace {
JITCodeEmitter &MCE; JITCodeEmitter &MCE;
MachineModuleInfo *MMI; MachineModuleInfo *MMI;
void getAnalysisUsage(AnalysisUsage &AU) const { void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired<MachineModuleInfo>(); AU.addRequired<MachineModuleInfo>();
MachineFunctionPass::getAnalysisUsage(AU); MachineFunctionPass::getAnalysisUsage(AU);
} }
@ -73,11 +73,13 @@ namespace {
unsigned getTLSRegEncoding(const MachineInstr &MI, unsigned OpNo) const; unsigned getTLSRegEncoding(const MachineInstr &MI, unsigned OpNo) const;
unsigned getTLSCallEncoding(const MachineInstr &MI, unsigned OpNo) const; unsigned getTLSCallEncoding(const MachineInstr &MI, unsigned OpNo) const;
const char *getPassName() const { return "PowerPC Machine Code Emitter"; } const char *getPassName() const override {
return "PowerPC Machine Code Emitter";
}
/// runOnMachineFunction - emits the given MachineFunction to memory /// runOnMachineFunction - emits the given MachineFunction to memory
/// ///
bool runOnMachineFunction(MachineFunction &MF); bool runOnMachineFunction(MachineFunction &MF) override;
/// emitBasicBlock - emits the given MachineBasicBlock to memory /// emitBasicBlock - emits the given MachineBasicBlock to memory
/// ///

36
lib/Target/PowerPC/PPCFastISel.cpp
View File

@ -103,24 +103,24 @@ class PPCFastISel final : public FastISel {
// Backend specific FastISel code. // Backend specific FastISel code.
private: private:
virtual bool TargetSelectInstruction(const Instruction *I); bool TargetSelectInstruction(const Instruction *I) override;
virtual unsigned TargetMaterializeConstant(const Constant *C); unsigned TargetMaterializeConstant(const Constant *C) override;
virtual unsigned TargetMaterializeAlloca(const AllocaInst *AI); unsigned TargetMaterializeAlloca(const AllocaInst *AI) override;
virtual bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo, bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
const LoadInst *LI); const LoadInst *LI) override;
virtual bool FastLowerArguments(); bool FastLowerArguments() override;
virtual unsigned FastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm); unsigned FastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm) override;
virtual unsigned FastEmitInst_ri(unsigned MachineInstOpcode, unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
unsigned Op0, bool Op0IsKill, unsigned Op0, bool Op0IsKill,
uint64_t Imm); uint64_t Imm);
virtual unsigned FastEmitInst_r(unsigned MachineInstOpcode, unsigned FastEmitInst_r(unsigned MachineInstOpcode,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
unsigned Op0, bool Op0IsKill); unsigned Op0, bool Op0IsKill);
virtual unsigned FastEmitInst_rr(unsigned MachineInstOpcode, unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
unsigned Op0, bool Op0IsKill, unsigned Op0, bool Op0IsKill,
unsigned Op1, bool Op1IsKill); unsigned Op1, bool Op1IsKill);
// Instruction selection routines. // Instruction selection routines.
private: private:

26
lib/Target/PowerPC/PPCFrameLowering.h
View File

@ -38,37 +38,37 @@ public:
/// emitProlog/emitEpilog - These methods insert prolog and epilog code into /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
/// the function. /// the function.
void emitPrologue(MachineFunction &MF) const; void emitPrologue(MachineFunction &MF) const override;
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
bool hasFP(const MachineFunction &MF) const; bool hasFP(const MachineFunction &MF) const override;
bool needsFP(const MachineFunction &MF) const; bool needsFP(const MachineFunction &MF) const;
void replaceFPWithRealFP(MachineFunction &MF) const; void replaceFPWithRealFP(MachineFunction &MF) const;
void processFunctionBeforeCalleeSavedScan(MachineFunction &MF, void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
RegScavenger *RS = nullptr) const; RegScavenger *RS = nullptr) const override;
void processFunctionBeforeFrameFinalized(MachineFunction &MF, void processFunctionBeforeFrameFinalized(MachineFunction &MF,
RegScavenger *RS = nullptr) const; RegScavenger *RS = nullptr) const override;
void addScavengingSpillSlot(MachineFunction &MF, RegScavenger *RS) const; void addScavengingSpillSlot(MachineFunction &MF, RegScavenger *RS) const;
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI, const std::vector<CalleeSavedInfo> &CSI,
const TargetRegisterInfo *TRI) const; const TargetRegisterInfo *TRI) const override;
void eliminateCallFramePseudoInstr(MachineFunction &MF, void eliminateCallFramePseudoInstr(MachineFunction &MF,
MachineBasicBlock &MBB, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const; MachineBasicBlock::iterator I) const override;
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI, const std::vector<CalleeSavedInfo> &CSI,
const TargetRegisterInfo *TRI) const; const TargetRegisterInfo *TRI) const override;
/// targetHandlesStackFrameRounding - Returns true if the target is /// targetHandlesStackFrameRounding - Returns true if the target is
/// responsible for rounding up the stack frame (probably at emitPrologue /// responsible for rounding up the stack frame (probably at emitPrologue
/// time). /// time).
bool targetHandlesStackFrameRounding() const { return true; } bool targetHandlesStackFrameRounding() const override { return true; }
/// getReturnSaveOffset - Return the previous frame offset to save the /// getReturnSaveOffset - Return the previous frame offset to save the
/// return address. /// return address.
@ -141,7 +141,7 @@ public:
// With the SVR4 ABI, callee-saved registers have fixed offsets on the stack. // With the SVR4 ABI, callee-saved registers have fixed offsets on the stack.
const SpillSlot * const SpillSlot *
getCalleeSavedSpillSlots(unsigned &NumEntries) const { getCalleeSavedSpillSlots(unsigned &NumEntries) const override {
if (Subtarget.isDarwinABI()) { if (Subtarget.isDarwinABI()) {
NumEntries = 1; NumEntries = 1;
if (Subtarget.isPPC64()) { if (Subtarget.isPPC64()) {

24
lib/Target/PowerPC/PPCHazardRecognizers.h
View File

@ -37,14 +37,14 @@ public:
ScoreboardHazardRecognizer(ItinData, DAG_), DAG(DAG_), ScoreboardHazardRecognizer(ItinData, DAG_), DAG(DAG_),
CurSlots(0), CurBranches(0) {} CurSlots(0), CurBranches(0) {}
virtual HazardType getHazardType(SUnit *SU, int Stalls); HazardType getHazardType(SUnit *SU, int Stalls) override;
virtual bool ShouldPreferAnother(SUnit* SU); bool ShouldPreferAnother(SUnit* SU) override;
virtual unsigned PreEmitNoops(SUnit *SU); unsigned PreEmitNoops(SUnit *SU) override;
virtual void EmitInstruction(SUnit *SU); void EmitInstruction(SUnit *SU) override;
virtual void AdvanceCycle(); void AdvanceCycle() override;
virtual void RecedeCycle(); void RecedeCycle() override;
virtual void Reset(); void Reset() override;
virtual void EmitNoop(); void EmitNoop() override;
}; };
/// PPCHazardRecognizer970 - This class defines a finite state automata that /// PPCHazardRecognizer970 - This class defines a finite state automata that
@ -76,10 +76,10 @@ class PPCHazardRecognizer970 : public ScheduleHazardRecognizer {
public: public:
PPCHazardRecognizer970(const TargetMachine &TM); PPCHazardRecognizer970(const TargetMachine &TM);
virtual HazardType getHazardType(SUnit *SU, int Stalls); virtual HazardType getHazardType(SUnit *SU, int Stalls) override;
virtual void EmitInstruction(SUnit *SU); virtual void EmitInstruction(SUnit *SU) override;
virtual void AdvanceCycle(); virtual void AdvanceCycle() override;
virtual void Reset(); virtual void Reset() override;
private: private:
/// EndDispatchGroup - Called when we are finishing a new dispatch group. /// EndDispatchGroup - Called when we are finishing a new dispatch group.

14
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
View File

@ -62,7 +62,7 @@ namespace {
initializePPCDAGToDAGISelPass(*PassRegistry::getPassRegistry()); initializePPCDAGToDAGISelPass(*PassRegistry::getPassRegistry());
} }
virtual bool runOnMachineFunction(MachineFunction &MF) { bool runOnMachineFunction(MachineFunction &MF) override {
// Make sure we re-emit a set of the global base reg if necessary // Make sure we re-emit a set of the global base reg if necessary
GlobalBaseReg = 0; GlobalBaseReg = 0;
SelectionDAGISel::runOnMachineFunction(MF); SelectionDAGISel::runOnMachineFunction(MF);
@ -73,7 +73,7 @@ namespace {
return true; return true;
} }
virtual void PostprocessISelDAG(); void PostprocessISelDAG() override;
/// getI32Imm - Return a target constant with the specified value, of type /// getI32Imm - Return a target constant with the specified value, of type
/// i32. /// i32.
@ -110,7 +110,7 @@ namespace {
// Select - Convert the specified operand from a target-independent to a // Select - Convert the specified operand from a target-independent to a
// target-specific node if it hasn't already been changed. // target-specific node if it hasn't already been changed.
SDNode *Select(SDNode *N); SDNode *Select(SDNode *N) override;
SDNode *SelectBitfieldInsert(SDNode *N); SDNode *SelectBitfieldInsert(SDNode *N);
@ -169,16 +169,16 @@ namespace {
/// a register. The case of adding a (possibly relocatable) constant to a /// a register. The case of adding a (possibly relocatable) constant to a
/// register can be improved, but it is wrong to substitute Reg+Reg for /// register can be improved, but it is wrong to substitute Reg+Reg for
/// Reg in an asm, because the load or store opcode would have to change. /// Reg in an asm, because the load or store opcode would have to change.
virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, bool SelectInlineAsmMemoryOperand(const SDValue &Op,
char ConstraintCode, char ConstraintCode,
std::vector<SDValue> &OutOps) { std::vector<SDValue> &OutOps) override {
OutOps.push_back(Op); OutOps.push_back(Op);
return false; return false;
} }
void InsertVRSaveCode(MachineFunction &MF); void InsertVRSaveCode(MachineFunction &MF);
virtual const char *getPassName() const { const char *getPassName() const override {
return "PowerPC DAG->DAG Pattern Instruction Selection"; return "PowerPC DAG->DAG Pattern Instruction Selection";
} }

95
lib/Target/PowerPC/PPCISelLowering.h
View File

@ -351,20 +351,20 @@ namespace llvm {
/// getTargetNodeName() - This method returns the name of a target specific /// getTargetNodeName() - This method returns the name of a target specific
/// DAG node. /// DAG node.
virtual const char *getTargetNodeName(unsigned Opcode) const; const char *getTargetNodeName(unsigned Opcode) const override;
virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; } MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; }
/// getSetCCResultType - Return the ISD::SETCC ValueType /// getSetCCResultType - Return the ISD::SETCC ValueType
virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const; EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
/// getPreIndexedAddressParts - returns true by value, base pointer and /// getPreIndexedAddressParts - returns true by value, base pointer and
/// offset pointer and addressing mode by reference if the node's address /// offset pointer and addressing mode by reference if the node's address
/// can be legally represented as pre-indexed load / store address. /// can be legally represented as pre-indexed load / store address.
virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
SDValue &Offset, SDValue &Offset,
ISD::MemIndexedMode &AM, ISD::MemIndexedMode &AM,
SelectionDAG &DAG) const; SelectionDAG &DAG) const override;
/// SelectAddressRegReg - Given the specified addressed, check to see if it /// SelectAddressRegReg - Given the specified addressed, check to see if it
/// can be represented as an indexed [r+r] operation. Returns false if it /// can be represented as an indexed [r+r] operation. Returns false if it
@ -384,29 +384,29 @@ namespace llvm {
bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index, bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
SelectionDAG &DAG) const; SelectionDAG &DAG) const;
Sched::Preference getSchedulingPreference(SDNode *N) const; Sched::Preference getSchedulingPreference(SDNode *N) const override;
/// LowerOperation - Provide custom lowering hooks for some operations. /// LowerOperation - Provide custom lowering hooks for some operations.
/// ///
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
/// ReplaceNodeResults - Replace the results of node with an illegal result /// ReplaceNodeResults - Replace the results of node with an illegal result
/// type with new values built out of custom code. /// type with new values built out of custom code.
/// ///
virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
SelectionDAG &DAG) const; SelectionDAG &DAG) const override;
virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
virtual void computeMaskedBitsForTargetNode(const SDValue Op, void computeMaskedBitsForTargetNode(const SDValue Op,
APInt &KnownZero, APInt &KnownZero,
APInt &KnownOne, APInt &KnownOne,
const SelectionDAG &DAG, const SelectionDAG &DAG,
unsigned Depth = 0) const; unsigned Depth = 0) const override;
virtual MachineBasicBlock * MachineBasicBlock *
EmitInstrWithCustomInserter(MachineInstr *MI, EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *MBB) const; MachineBasicBlock *MBB) const override;
MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
MachineBasicBlock *MBB, bool is64Bit, MachineBasicBlock *MBB, bool is64Bit,
unsigned BinOpcode) const; unsigned BinOpcode) const;
@ -420,32 +420,33 @@ namespace llvm {
MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI, MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
MachineBasicBlock *MBB) const; MachineBasicBlock *MBB) const;
ConstraintType getConstraintType(const std::string &Constraint) const; ConstraintType
getConstraintType(const std::string &Constraint) const override;
/// Examine constraint string and operand type and determine a weight value. /// Examine constraint string and operand type and determine a weight value.
/// The operand object must already have been set up with the operand type. /// The operand object must already have been set up with the operand type.
ConstraintWeight getSingleConstraintMatchWeight( ConstraintWeight getSingleConstraintMatchWeight(
AsmOperandInfo &info, const char *constraint) const; AsmOperandInfo &info, const char *constraint) const override;
std::pair<unsigned, const TargetRegisterClass*> std::pair<unsigned, const TargetRegisterClass*>
getRegForInlineAsmConstraint(const std::string &Constraint, getRegForInlineAsmConstraint(const std::string &Constraint,
MVT VT) const; MVT VT) const override;
/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
/// function arguments in the caller parameter area. This is the actual /// function arguments in the caller parameter area. This is the actual
/// alignment, not its logarithm. /// alignment, not its logarithm.
unsigned getByValTypeAlignment(Type *Ty) const; unsigned getByValTypeAlignment(Type *Ty) const override;
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
/// vector. If it is invalid, don't add anything to Ops. /// vector. If it is invalid, don't add anything to Ops.
virtual void LowerAsmOperandForConstraint(SDValue Op, void LowerAsmOperandForConstraint(SDValue Op,
std::string &Constraint, std::string &Constraint,
std::vector<SDValue> &Ops, std::vector<SDValue> &Ops,
SelectionDAG &DAG) const; SelectionDAG &DAG) const override;
/// isLegalAddressingMode - Return true if the addressing mode represented /// isLegalAddressingMode - Return true if the addressing mode represented
/// by AM is legal for this target, for a load/store of the specified type. /// by AM is legal for this target, for a load/store of the specified type.
virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const; bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
/// isLegalICmpImmediate - Return true if the specified immediate is legal /// isLegalICmpImmediate - Return true if the specified immediate is legal
/// icmp immediate, that is the target has icmp instructions which can /// icmp immediate, that is the target has icmp instructions which can
@ -470,7 +471,7 @@ namespace llvm {
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
Type *Ty) const override; Type *Ty) const override;
virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
/// getOptimalMemOpType - Returns the target specific optimal type for load /// getOptimalMemOpType - Returns the target specific optimal type for load
/// and store operations as a result of memset, memcpy, and memmove /// and store operations as a result of memset, memcpy, and memmove
@ -483,32 +484,32 @@ namespace llvm {
/// source is constant so it does not need to be loaded. /// source is constant so it does not need to be loaded.
/// It returns EVT::Other if the type should be determined using generic /// It returns EVT::Other if the type should be determined using generic
/// target-independent logic. /// target-independent logic.
virtual EVT EVT
getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
MachineFunction &MF) const; MachineFunction &MF) const override;
/// Is unaligned memory access allowed for the given type, and is it fast /// Is unaligned memory access allowed for the given type, and is it fast
/// relative to software emulation. /// relative to software emulation.
virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool allowsUnalignedMemoryAccesses(EVT VT,
unsigned AddrSpace, unsigned AddrSpace,
bool *Fast = nullptr) const; bool *Fast = nullptr) const override;
/// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
/// than a pair of fmul and fadd instructions. fmuladd intrinsics will be /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
/// expanded to FMAs when this method returns true, otherwise fmuladd is /// expanded to FMAs when this method returns true, otherwise fmuladd is
/// expanded to fmul + fadd. /// expanded to fmul + fadd.
virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const; bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
// Should we expand the build vector with shuffles? // Should we expand the build vector with shuffles?
virtual bool bool
shouldExpandBuildVectorWithShuffles(EVT VT, shouldExpandBuildVectorWithShuffles(EVT VT,
unsigned DefinedValues) const; unsigned DefinedValues) const override;
/// createFastISel - This method returns a target-specific FastISel object, /// createFastISel - This method returns a target-specific FastISel object,
/// or null if the target does not support "fast" instruction selection. /// or null if the target does not support "fast" instruction selection.
virtual FastISel *createFastISel(FunctionLoweringInfo &FuncInfo, FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
const TargetLibraryInfo *LibInfo) const; const TargetLibraryInfo *LibInfo) const override;
private: private:
SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const; SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
@ -582,29 +583,29 @@ namespace llvm {
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
SmallVectorImpl<SDValue> &InVals) const; SmallVectorImpl<SDValue> &InVals) const;
virtual SDValue SDValue
LowerFormalArguments(SDValue Chain, LowerFormalArguments(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
SDLoc dl, SelectionDAG &DAG, SDLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const; SmallVectorImpl<SDValue> &InVals) const override;
virtual SDValue SDValue
LowerCall(TargetLowering::CallLoweringInfo &CLI, LowerCall(TargetLowering::CallLoweringInfo &CLI,
SmallVectorImpl<SDValue> &InVals) const; SmallVectorImpl<SDValue> &InVals) const override;
virtual bool bool
CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
bool isVarArg, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
LLVMContext &Context) const; LLVMContext &Context) const override;
virtual SDValue SDValue
LowerReturn(SDValue Chain, LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<SDValue> &OutVals,
SDLoc dl, SelectionDAG &DAG) const; SDLoc dl, SelectionDAG &DAG) const override;
SDValue SDValue
extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, SelectionDAG &DAG, extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, SelectionDAG &DAG,

16
lib/Target/PowerPC/PPCInstrInfo.cpp
View File

@ -1812,7 +1812,7 @@ protected:
} }
public: public:
virtual bool runOnMachineFunction(MachineFunction &MF) { bool runOnMachineFunction(MachineFunction &MF) override {
LIS = &getAnalysis<LiveIntervals>(); LIS = &getAnalysis<LiveIntervals>();
TM = static_cast<const PPCTargetMachine *>(&MF.getTarget()); TM = static_cast<const PPCTargetMachine *>(&MF.getTarget());
@ -1832,7 +1832,7 @@ public:
return Changed; return Changed;
} }
virtual void getAnalysisUsage(AnalysisUsage &AU) const { void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired<LiveIntervals>(); AU.addRequired<LiveIntervals>();
AU.addPreserved<LiveIntervals>(); AU.addPreserved<LiveIntervals>();
AU.addRequired<SlotIndexes>(); AU.addRequired<SlotIndexes>();
@ -1964,7 +1964,7 @@ protected:
} }
public: public:
virtual bool runOnMachineFunction(MachineFunction &MF) { bool runOnMachineFunction(MachineFunction &MF) override {
TM = static_cast<const PPCTargetMachine *>(&MF.getTarget()); TM = static_cast<const PPCTargetMachine *>(&MF.getTarget());
TII = TM->getInstrInfo(); TII = TM->getInstrInfo();
@ -1979,7 +1979,7 @@ public:
return Changed; return Changed;
} }
virtual void getAnalysisUsage(AnalysisUsage &AU) const { void getAnalysisUsage(AnalysisUsage &AU) const override {
MachineFunctionPass::getAnalysisUsage(AU); MachineFunctionPass::getAnalysisUsage(AU);
} }
}; };
@ -2038,7 +2038,7 @@ protected:
} }
public: public:
virtual bool runOnMachineFunction(MachineFunction &MF) { bool runOnMachineFunction(MachineFunction &MF) override {
TM = static_cast<const PPCTargetMachine *>(&MF.getTarget()); TM = static_cast<const PPCTargetMachine *>(&MF.getTarget());
TII = TM->getInstrInfo(); TII = TM->getInstrInfo();
@ -2053,7 +2053,7 @@ public:
return Changed; return Changed;
} }
virtual void getAnalysisUsage(AnalysisUsage &AU) const { void getAnalysisUsage(AnalysisUsage &AU) const override {
MachineFunctionPass::getAnalysisUsage(AU); MachineFunctionPass::getAnalysisUsage(AU);
} }
}; };
@ -2195,7 +2195,7 @@ protected:
} }
public: public:
virtual bool runOnMachineFunction(MachineFunction &MF) { bool runOnMachineFunction(MachineFunction &MF) override {
TM = static_cast<const PPCTargetMachine *>(&MF.getTarget()); TM = static_cast<const PPCTargetMachine *>(&MF.getTarget());
TII = TM->getInstrInfo(); TII = TM->getInstrInfo();
@ -2215,7 +2215,7 @@ public:
return Changed; return Changed;
} }
virtual void getAnalysisUsage(AnalysisUsage &AU) const { void getAnalysisUsage(AnalysisUsage &AU) const override {
MachineFunctionPass::getAnalysisUsage(AU); MachineFunctionPass::getAnalysisUsage(AU);
} }
}; };

159
lib/Target/PowerPC/PPCInstrInfo.h
View File

@ -86,151 +86,148 @@ public:
/// such, whenever a client has an instance of instruction info, it should /// such, whenever a client has an instance of instruction info, it should
/// always be able to get register info as well (through this method). /// always be able to get register info as well (through this method).
/// ///
virtual const PPCRegisterInfo &getRegisterInfo() const { return RI; } const PPCRegisterInfo &getRegisterInfo() const { return RI; }
ScheduleHazardRecognizer * ScheduleHazardRecognizer *
CreateTargetHazardRecognizer(const TargetMachine *TM, CreateTargetHazardRecognizer(const TargetMachine *TM,
const ScheduleDAG *DAG) const; const ScheduleDAG *DAG) const override;
ScheduleHazardRecognizer * ScheduleHazardRecognizer *
CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
const ScheduleDAG *DAG) const; const ScheduleDAG *DAG) const override;
virtual
int getOperandLatency(const InstrItineraryData *ItinData, int getOperandLatency(const InstrItineraryData *ItinData,
const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *DefMI, unsigned DefIdx,
const MachineInstr *UseMI, unsigned UseIdx) const; const MachineInstr *UseMI,
virtual unsigned UseIdx) const override;
int getOperandLatency(const InstrItineraryData *ItinData, int getOperandLatency(const InstrItineraryData *ItinData,
SDNode *DefNode, unsigned DefIdx, SDNode *DefNode, unsigned DefIdx,
SDNode *UseNode, unsigned UseIdx) const { SDNode *UseNode, unsigned UseIdx) const override {
return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx, return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx,
UseNode, UseIdx); UseNode, UseIdx);
} }
bool isCoalescableExtInstr(const MachineInstr &MI, bool isCoalescableExtInstr(const MachineInstr &MI,
unsigned &SrcReg, unsigned &DstReg, unsigned &SrcReg, unsigned &DstReg,
unsigned &SubIdx) const; unsigned &SubIdx) const override;
unsigned isLoadFromStackSlot(const MachineInstr *MI, unsigned isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const; int &FrameIndex) const override;
unsigned isStoreToStackSlot(const MachineInstr *MI, unsigned isStoreToStackSlot(const MachineInstr *MI,
int &FrameIndex) const; int &FrameIndex) const override;
// commuteInstruction - We can commute rlwimi instructions, but only if the // commuteInstruction - We can commute rlwimi instructions, but only if the
// rotate amt is zero. We also have to munge the immediates a bit. // rotate amt is zero. We also have to munge the immediates a bit.
virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const; MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const override;
virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
unsigned &SrcOpIdx2) const; unsigned &SrcOpIdx2) const override;
virtual void insertNoop(MachineBasicBlock &MBB, void insertNoop(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const; MachineBasicBlock::iterator MI) const override;
// Branch analysis. // Branch analysis.
virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB, MachineBasicBlock *&FBB,
SmallVectorImpl<MachineOperand> &Cond, SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify) const; bool AllowModify) const override;
virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond, const SmallVectorImpl<MachineOperand> &Cond,
DebugLoc DL) const; DebugLoc DL) const override;
// Select analysis. // Select analysis.
virtual bool canInsertSelect(const MachineBasicBlock&, bool canInsertSelect(const MachineBasicBlock&,
const SmallVectorImpl<MachineOperand> &Cond, const SmallVectorImpl<MachineOperand> &Cond,
unsigned, unsigned, int&, int&, int&) const; unsigned, unsigned, int&, int&, int&) const override;
virtual void insertSelect(MachineBasicBlock &MBB, void insertSelect(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, DebugLoc DL, MachineBasicBlock::iterator MI, DebugLoc DL,
unsigned DstReg, unsigned DstReg,
const SmallVectorImpl<MachineOperand> &Cond, const SmallVectorImpl<MachineOperand> &Cond,
unsigned TrueReg, unsigned FalseReg) const; unsigned TrueReg, unsigned FalseReg) const override;
virtual void copyPhysReg(MachineBasicBlock &MBB, void copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, DebugLoc DL, MachineBasicBlock::iterator I, DebugLoc DL,
unsigned DestReg, unsigned SrcReg, unsigned DestReg, unsigned SrcReg,
bool KillSrc) const; bool KillSrc) const override;
virtual void storeRegToStackSlot(MachineBasicBlock &MBB, void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, MachineBasicBlock::iterator MBBI,
unsigned SrcReg, bool isKill, int FrameIndex, unsigned SrcReg, bool isKill, int FrameIndex,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const; const TargetRegisterInfo *TRI) const override;
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, void loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, MachineBasicBlock::iterator MBBI,
unsigned DestReg, int FrameIndex, unsigned DestReg, int FrameIndex,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const; const TargetRegisterInfo *TRI) const override;
virtual bool
bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
unsigned Reg, MachineRegisterInfo *MRI) const; unsigned Reg, MachineRegisterInfo *MRI) const override;
// If conversion by predication (only supported by some branch instructions). // If conversion by predication (only supported by some branch instructions).
// All of the profitability checks always return true; it is always // All of the profitability checks always return true; it is always
// profitable to use the predicated branches. // profitable to use the predicated branches.
virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, bool isProfitableToIfCvt(MachineBasicBlock &MBB,
unsigned NumCycles, unsigned ExtraPredCycles, unsigned NumCycles, unsigned ExtraPredCycles,
const BranchProbability &Probability) const { const BranchProbability &Probability) const override {
return true; return true;
} }
virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
unsigned NumT, unsigned ExtraT, unsigned NumT, unsigned ExtraT,
MachineBasicBlock &FMBB, MachineBasicBlock &FMBB,
unsigned NumF, unsigned ExtraF, unsigned NumF, unsigned ExtraF,
const BranchProbability &Probability) const; const BranchProbability &Probability) const override;
virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
unsigned NumCycles, unsigned NumCycles,
const BranchProbability const BranchProbability
&Probability) const { &Probability) const override {
return true; return true;
} }
virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
MachineBasicBlock &FMBB) const { MachineBasicBlock &FMBB) const override {
return false; return false;
} }
// Predication support. // Predication support.
bool isPredicated(const MachineInstr *MI) const; bool isPredicated(const MachineInstr *MI) const override;
virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; bool isUnpredicatedTerminator(const MachineInstr *MI) const override;
virtual
bool PredicateInstruction(MachineInstr *MI, bool PredicateInstruction(MachineInstr *MI,
const SmallVectorImpl<MachineOperand> &Pred) const; const SmallVectorImpl<MachineOperand> &Pred) const override;
virtual
bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
const SmallVectorImpl<MachineOperand> &Pred2) const; const SmallVectorImpl<MachineOperand> &Pred2) const override;
virtual bool DefinesPredicate(MachineInstr *MI, bool DefinesPredicate(MachineInstr *MI,
std::vector<MachineOperand> &Pred) const; std::vector<MachineOperand> &Pred) const override;
virtual bool isPredicable(MachineInstr *MI) const; bool isPredicable(MachineInstr *MI) const override;
// Comparison optimization. // Comparison optimization.
virtual bool analyzeCompare(const MachineInstr *MI, bool analyzeCompare(const MachineInstr *MI,
unsigned &SrcReg, unsigned &SrcReg2, unsigned &SrcReg, unsigned &SrcReg2,
int &Mask, int &Value) const; int &Mask, int &Value) const override;
virtual bool optimizeCompareInstr(MachineInstr *CmpInstr, bool optimizeCompareInstr(MachineInstr *CmpInstr,
unsigned SrcReg, unsigned SrcReg2, unsigned SrcReg, unsigned SrcReg2,
int Mask, int Value, int Mask, int Value,
const MachineRegisterInfo *MRI) const; const MachineRegisterInfo *MRI) const override;
/// GetInstSize - Return the number of bytes of code the specified /// GetInstSize - Return the number of bytes of code the specified
/// instruction may be. This returns the maximum number of bytes. /// instruction may be. This returns the maximum number of bytes.
/// ///
virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const; virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const final;
}; };
} }

16
lib/Target/PowerPC/PPCJITInfo.h
View File

@ -30,19 +30,19 @@ namespace llvm {
is64Bit = tmIs64Bit; is64Bit = tmIs64Bit;
} }
virtual StubLayout getStubLayout(); StubLayout getStubLayout() override;
virtual void *emitFunctionStub(const Function* F, void *Fn, void *emitFunctionStub(const Function* F, void *Fn,
JITCodeEmitter &JCE); JITCodeEmitter &JCE) override;
virtual LazyResolverFn getLazyResolverFunction(JITCompilerFn); LazyResolverFn getLazyResolverFunction(JITCompilerFn) override;
virtual void relocate(void *Function, MachineRelocation *MR, void relocate(void *Function, MachineRelocation *MR,
unsigned NumRelocs, unsigned char* GOTBase); unsigned NumRelocs, unsigned char* GOTBase) override;
/// replaceMachineCodeForFunction - Make it so that calling the function /// replaceMachineCodeForFunction - Make it so that calling the function
/// whose machine code is at OLD turns into a call to NEW, perhaps by /// whose machine code is at OLD turns into a call to NEW, perhaps by
/// overwriting OLD with a branch to NEW. This is used for self-modifying /// overwriting OLD with a branch to NEW. This is used for self-modifying
/// code. /// code.
/// ///
virtual void replaceMachineCodeForFunction(void *Old, void *New); void replaceMachineCodeForFunction(void *Old, void *New) override;
}; };
} }

40
lib/Target/PowerPC/PPCRegisterInfo.h
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@ -34,36 +34,37 @@ public:
/// getPointerRegClass - Return the register class to use to hold pointers. /// getPointerRegClass - Return the register class to use to hold pointers.
/// This is used for addressing modes. /// This is used for addressing modes.
virtual const TargetRegisterClass * const TargetRegisterClass *
getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const; getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override;
unsigned getRegPressureLimit(const TargetRegisterClass *RC, unsigned getRegPressureLimit(const TargetRegisterClass *RC,
MachineFunction &MF) const; MachineFunction &MF) const override;
const TargetRegisterClass* const TargetRegisterClass*
getLargestLegalSuperClass(const TargetRegisterClass *RC) const; getLargestLegalSuperClass(const TargetRegisterClass *RC) const override;
/// Code Generation virtual methods... /// Code Generation virtual methods...
const MCPhysReg *getCalleeSavedRegs(const MachineFunction* MF =nullptr) const; const MCPhysReg *
const uint32_t *getCallPreservedMask(CallingConv::ID CC) const; getCalleeSavedRegs(const MachineFunction* MF =nullptr) const override;
const uint32_t *getCallPreservedMask(CallingConv::ID CC) const override;
const uint32_t *getNoPreservedMask() const; const uint32_t *getNoPreservedMask() const;
BitVector getReservedRegs(const MachineFunction &MF) const; BitVector getReservedRegs(const MachineFunction &MF) const override;
/// We require the register scavenger. /// We require the register scavenger.
bool requiresRegisterScavenging(const MachineFunction &MF) const { bool requiresRegisterScavenging(const MachineFunction &MF) const override {
return true; return true;
} }
bool requiresFrameIndexScavenging(const MachineFunction &MF) const { bool requiresFrameIndexScavenging(const MachineFunction &MF) const override {
return true; return true;
} }
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const { bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override {
return true; return true;
} }
virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const { bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override {
return true; return true;
} }
@ -82,28 +83,29 @@ public:
unsigned FrameIndex) const; unsigned FrameIndex) const;
bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
int &FrameIdx) const; int &FrameIdx) const override;
void eliminateFrameIndex(MachineBasicBlock::iterator II, void eliminateFrameIndex(MachineBasicBlock::iterator II,
int SPAdj, unsigned FIOperandNum, int SPAdj, unsigned FIOperandNum,
RegScavenger *RS = nullptr) const; RegScavenger *RS = nullptr) const override;
// Support for virtual base registers. // Support for virtual base registers.
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const; bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
void materializeFrameBaseRegister(MachineBasicBlock *MBB, void materializeFrameBaseRegister(MachineBasicBlock *MBB,
unsigned BaseReg, int FrameIdx, unsigned BaseReg, int FrameIdx,
int64_t Offset) const; int64_t Offset) const override;
void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
int64_t Offset) const; int64_t Offset) const override;
bool isFrameOffsetLegal(const MachineInstr *MI, int64_t Offset) const; bool isFrameOffsetLegal(const MachineInstr *MI,
int64_t Offset) const override;
// Debug information queries. // Debug information queries.
unsigned getFrameRegister(const MachineFunction &MF) const; unsigned getFrameRegister(const MachineFunction &MF) const override;
// Base pointer (stack realignment) support. // Base pointer (stack realignment) support.
unsigned getBaseRegister(const MachineFunction &MF) const; unsigned getBaseRegister(const MachineFunction &MF) const;
bool hasBasePointer(const MachineFunction &MF) const; bool hasBasePointer(const MachineFunction &MF) const;
bool canRealignStack(const MachineFunction &MF) const; bool canRealignStack(const MachineFunction &MF) const;
bool needsStackRealignment(const MachineFunction &MF) const; bool needsStackRealignment(const MachineFunction &MF) const override;
}; };
} // end namespace llvm } // end namespace llvm

10
lib/Target/PowerPC/PPCSubtarget.h
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@ -129,7 +129,7 @@ public:
const InstrItineraryData &getInstrItineraryData() const { return InstrItins; } const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
/// \brief Reset the features for the PowerPC target. /// \brief Reset the features for the PowerPC target.
virtual void resetSubtargetFeatures(const MachineFunction *MF); void resetSubtargetFeatures(const MachineFunction *MF) override;
private: private:
void initializeEnvironment(); void initializeEnvironment();
void resetSubtargetFeatures(StringRef CPU, StringRef FS); void resetSubtargetFeatures(StringRef CPU, StringRef FS);
@ -200,15 +200,15 @@ public:
/// enablePostRAScheduler - True at 'More' optimization. /// enablePostRAScheduler - True at 'More' optimization.
bool enablePostRAScheduler(CodeGenOpt::Level OptLevel, bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
TargetSubtargetInfo::AntiDepBreakMode& Mode, TargetSubtargetInfo::AntiDepBreakMode& Mode,
RegClassVector& CriticalPathRCs) const; RegClassVector& CriticalPathRCs) const override;
// Scheduling customization. // Scheduling customization.
bool enableMachineScheduler() const; bool enableMachineScheduler() const override;
void overrideSchedPolicy(MachineSchedPolicy &Policy, void overrideSchedPolicy(MachineSchedPolicy &Policy,
MachineInstr *begin, MachineInstr *begin,
MachineInstr *end, MachineInstr *end,
unsigned NumRegionInstrs) const; unsigned NumRegionInstrs) const override;
bool useAA() const; bool useAA() const override;
}; };
} // End llvm namespace } // End llvm namespace

12
lib/Target/PowerPC/PPCTargetMachine.cpp
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@ -127,12 +127,12 @@ public:
return *getPPCTargetMachine().getSubtargetImpl(); return *getPPCTargetMachine().getSubtargetImpl();
} }
virtual bool addPreISel(); bool addPreISel() override;
virtual bool addILPOpts(); bool addILPOpts() override;
virtual bool addInstSelector(); bool addInstSelector() override;
virtual bool addPreRegAlloc(); bool addPreRegAlloc() override;
virtual bool addPreSched2(); bool addPreSched2() override;
virtual bool addPreEmitPass(); bool addPreEmitPass() override;
}; };
} // namespace } // namespace

26
lib/Target/PowerPC/PPCTargetMachine.h
View File

@ -43,34 +43,34 @@ public:
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL, bool is64Bit); CodeGenOpt::Level OL, bool is64Bit);
virtual const PPCInstrInfo *getInstrInfo() const { return &InstrInfo; } const PPCInstrInfo *getInstrInfo() const override { return &InstrInfo; }
virtual const PPCFrameLowering *getFrameLowering() const { const PPCFrameLowering *getFrameLowering() const override {
return &FrameLowering; return &FrameLowering;
} }
virtual PPCJITInfo *getJITInfo() { return &JITInfo; } PPCJITInfo *getJITInfo() override { return &JITInfo; }
virtual const PPCTargetLowering *getTargetLowering() const { const PPCTargetLowering *getTargetLowering() const override {
return &TLInfo; return &TLInfo;
} }
virtual const PPCSelectionDAGInfo* getSelectionDAGInfo() const { const PPCSelectionDAGInfo* getSelectionDAGInfo() const override {
return &TSInfo; return &TSInfo;
} }
virtual const PPCRegisterInfo *getRegisterInfo() const { const PPCRegisterInfo *getRegisterInfo() const override {
return &InstrInfo.getRegisterInfo(); return &InstrInfo.getRegisterInfo();
} }
virtual const DataLayout *getDataLayout() const { return &DL; } const DataLayout *getDataLayout() const override { return &DL; }
virtual const PPCSubtarget *getSubtargetImpl() const { return &Subtarget; } const PPCSubtarget *getSubtargetImpl() const override { return &Subtarget; }
virtual const InstrItineraryData *getInstrItineraryData() const { const InstrItineraryData *getInstrItineraryData() const override {
return &InstrItins; return &InstrItins;
} }
// Pass Pipeline Configuration // Pass Pipeline Configuration
virtual TargetPassConfig *createPassConfig(PassManagerBase &PM); TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
virtual bool addCodeEmitter(PassManagerBase &PM, bool addCodeEmitter(PassManagerBase &PM,
JITCodeEmitter &JCE); JITCodeEmitter &JCE) override;
/// \brief Register PPC analysis passes with a pass manager. /// \brief Register PPC analysis passes with a pass manager.
virtual void addAnalysisPasses(PassManagerBase &PM); void addAnalysisPasses(PassManagerBase &PM) override;
}; };
/// PPC32TargetMachine - PowerPC 32-bit target machine. /// PPC32TargetMachine - PowerPC 32-bit target machine.