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If triple is armv7 / thumbv7 and a CPU is specified, do not automatically assume

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the feature set of v7a. This comes about if the user specifies something like
-arch armv7 -mcpu=cortex-m3. We shouldn't be generating instructions such as
uxtab in this case.

rdar://11318438


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155601 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2012-04-26 01:13:36 +00:00
parent 4866363304
commit e67a4163f5
4 changed files with 30 additions and 14 deletions
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2
lib/Target/ARM/ARMSubtarget.cpp
View File

@ -83,7 +83,7 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
// Insert the architecture feature derived from the target triple into the
// feature string. This is important for setting features that are implied
// based on the architecture version.
std::string ArchFS = ARM_MC::ParseARMTriple(TT);
std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPUString);
if (!FS.empty()) {
if (!ArchFS.empty())
ArchFS = ArchFS + "," + FS;

19
lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
View File

@ -35,7 +35,7 @@
using namespace llvm;
std::string ARM_MC::ParseARMTriple(StringRef TT) {
std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) {
// Set the boolean corresponding to the current target triple, or the default
// if one cannot be determined, to true.
unsigned Len = TT.size();
@ -62,9 +62,18 @@ std::string ARM_MC::ParseARMTriple(StringRef TT) {
// v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
// FeatureT2XtPk, FeatureMClass
ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,t2xtpk,+mclass";
} else
// v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
ARMArchFeature = "+v7,+neon,+db,+t2dsp,+t2xtpk";
} else {
// v7 CPUs have lots of different feature sets. If no CPU is specified,
// then assume v7a (e.g. cortex-a8) feature set. Otherwise, return
// the "minimum" feature set and use CPU string to figure out the exact
// features.
if (CPU == "generic")
// v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
ARMArchFeature = "+v7,+neon,+db,+t2dsp,+t2xtpk";
else
// Use CPU to figure out the exact features.
ARMArchFeature = "+v7";
}
} else if (SubVer == '6') {
if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2')
ARMArchFeature = "+v6t2";
@ -94,7 +103,7 @@ std::string ARM_MC::ParseARMTriple(StringRef TT) {
MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
StringRef FS) {
std::string ArchFS = ARM_MC::ParseARMTriple(TT);
std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
if (!FS.empty()) {
if (!ArchFS.empty())
ArchFS = ArchFS + "," + FS.str();

2
lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
View File

@ -31,7 +31,7 @@ class raw_ostream;
extern Target TheARMTarget, TheThumbTarget;
namespace ARM_MC {
std::string ParseARMTriple(StringRef TT);
std::string ParseARMTriple(StringRef TT, StringRef CPU);
/// createARMMCSubtargetInfo - Create a ARM MCSubtargetInfo instance.
/// This is exposed so Asm parser, etc. do not need to go through

21
test/CodeGen/Thumb2/thumb2-uxt_rot.ll
View File

@ -1,15 +1,22 @@
; RUN: llc < %s -march=thumb -mattr=+thumb2,+t2xtpk | FileCheck %s
; RUN: llc < %s -march=thumb -mcpu=cortex-a8 | FileCheck %s --check-prefix=A8
; RUN: llc < %s -march=thumb -mcpu=cortex-m3 | FileCheck %s --check-prefix=M3
; rdar://11318438
define zeroext i8 @test1(i32 %A.u) {
; CHECK: test1
; CHECK: uxtb r0, r0
; A8: test1
; A8: uxtb r0, r0
%B.u = trunc i32 %A.u to i8
ret i8 %B.u
}
define zeroext i32 @test2(i32 %A.u, i32 %B.u) {
; CHECK: test2
; CHECK: uxtab r0, r0, r1
; A8: test2
; A8: uxtab r0, r0, r1
; M3: test2
; M3: uxtb r1, r1
; M3-NOT: uxtab
; M3: add r0, r1
%C.u = trunc i32 %B.u to i8
%D.u = zext i8 %C.u to i32
%E.u = add i32 %A.u, %D.u
@ -17,8 +24,8 @@ define zeroext i32 @test2(i32 %A.u, i32 %B.u) {
}
define zeroext i32 @test3(i32 %A.u) {
; CHECK: test3
; CHECK: uxth.w r0, r0, ror #8
; A8: test3
; A8: uxth.w r0, r0, ror #8
%B.u = lshr i32 %A.u, 8
%C.u = shl i32 %A.u, 24
%D.u = or i32 %B.u, %C.u