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enhance the load/store narrowing optimization to handle a

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tokenfactor in between the load/store.  This allows us to 
optimize test7 into:

_test7:                                 ## @test7
## BB#0:                                ## %entry
	movl	(%rdx), %eax
                                        ## kill: SIL<def> ESI<kill>
	movb	%sil, 5(%rdi)
	ret

instead of:

_test7:                                 ## @test7
## BB#0:                                ## %entry
	movl	4(%esp), %ecx
	movl	$-65281, %eax           ## imm = 0xFFFFFFFFFFFF00FF
	andl	4(%ecx), %eax
	movzbl	8(%esp), %edx
	shll	$8, %edx
	addl	%eax, %edx
	movl	12(%esp), %eax
	movl	(%eax), %eax
	movl	%edx, 4(%ecx)
	ret



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101355 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2010-04-15 06:10:49 +00:00
parent 6dc868581b
commit e6987587d6
2 changed files with 38 additions and 5 deletions
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23
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -5172,12 +5172,25 @@ CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) {
!ISD::isNormalLoad(V->getOperand(0).getNode()))
return Result;
// Check the chain and pointer. The store should be chained directly to the
// load (TODO: Or through a TF node!) since it's to the same address.
// Check the chain and pointer.
LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0));
if (LD->getBasePtr() != Ptr ||
V->getOperand(0).getNode() != Chain.getNode())
return Result;
if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer.
// The store should be chained directly to the load or be an operand of a
// tokenfactor.
if (LD == Chain.getNode())
; // ok.
else if (Chain->getOpcode() != ISD::TokenFactor)
return Result; // Fail.
else {
bool isOk = false;
for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i)
if (Chain->getOperand(i).getNode() == LD) {
isOk = true;
break;
}
if (!isOk) return Result;
}
// This only handles simple types.
if (V.getValueType() != MVT::i16 &&

20
test/CodeGen/X86/store-narrow.ll
View File

@ -105,3 +105,23 @@ entry:
; X32: movb 8(%esp), %al
; X32: movb %al, 5(%{{.*}})
}
define i32 @test7(i64* nocapture %a0, i8 zeroext %a1, i32* %P2) nounwind {
entry:
%OtherLoad = load i32 *%P2
%A = load i64* %a0, align 4
%B = and i64 %A, -280375465082881 ; 0xFFFF00FFFFFFFFFF
%C = zext i8 %a1 to i64
%CS = shl i64 %C, 40
%D = or i64 %B, %CS
store i64 %D, i64* %a0, align 4
ret i32 %OtherLoad
; X64: test7:
; X64: movb %sil, 5(%rdi)
; X32: test7:
; X32: movb 8(%esp), %cl
; X32: movb %cl, 5(%{{.*}})
}