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https://github.com/c64scene-ar/llvm-6502.git
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Spill and kill all virtual registers across a call.
Debug code doesn't use callee saved registers anyway, and the code is simpler this way. Now spillVirtReg always kills, and the isKill parameter is not needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103927 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
parent
01dcbf8507
commit
e6aba83797
@ -50,7 +50,7 @@ namespace {
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public:
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static char ID;
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RAFast() : MachineFunctionPass(&ID), StackSlotForVirtReg(-1),
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atEndOfBlock(false) {}
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isBulkSpilling(false) {}
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private:
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const TargetMachine *TM;
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MachineFunction *MF;
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@ -113,10 +113,10 @@ namespace {
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// Allocatable - vector of allocatable physical registers.
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BitVector Allocatable;
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// atEndOfBlock - This flag is set after allocating all instructions in a
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// block, before emitting final spills. When it is set, LiveRegMap is no
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// longer updated properly sonce it will be cleared anyway.
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bool atEndOfBlock;
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// isBulkSpilling - This flag is set when LiveRegMap will be cleared
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// completely after spilling all live registers. LiveRegMap entries should
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// not be erased.
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bool isBulkSpilling;
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public:
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virtual const char *getPassName() const {
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@ -139,10 +139,8 @@ namespace {
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void addKillFlag(const LiveReg&);
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void killVirtReg(LiveRegMap::iterator i);
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void killVirtReg(unsigned VirtReg);
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void spillVirtReg(MachineBasicBlock::iterator MI, LiveRegMap::iterator i,
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bool isKill);
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void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg,
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bool isKill);
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void spillVirtReg(MachineBasicBlock::iterator MI, LiveRegMap::iterator i);
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void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg);
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void usePhysReg(MachineOperand&);
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void definePhysReg(MachineInstr *MI, unsigned PhysReg, RegState NewState);
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@ -211,9 +209,8 @@ void RAFast::killVirtReg(LiveRegMap::iterator lri) {
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const LiveReg &LR = lri->second;
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assert(PhysRegState[LR.PhysReg] == lri->first && "Broken RegState mapping");
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PhysRegState[LR.PhysReg] = regFree;
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// Erase from LiveVirtRegs unless we're at the end of the block when
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// everything will be bulk erased.
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if (!atEndOfBlock)
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// Erase from LiveVirtRegs unless we're spilling in bulk.
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if (!isBulkSpilling)
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LiveVirtRegs.erase(lri);
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}
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@ -229,26 +226,24 @@ void RAFast::killVirtReg(unsigned VirtReg) {
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/// spillVirtReg - This method spills the value specified by VirtReg into the
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/// corresponding stack slot if needed. If isKill is set, the register is also
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/// killed.
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void RAFast::spillVirtReg(MachineBasicBlock::iterator MI,
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unsigned VirtReg, bool isKill) {
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void RAFast::spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg) {
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assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
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"Spilling a physical register is illegal!");
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LiveRegMap::iterator lri = LiveVirtRegs.find(VirtReg);
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assert(lri != LiveVirtRegs.end() && "Spilling unmapped virtual register");
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spillVirtReg(MI, lri, isKill);
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spillVirtReg(MI, lri);
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}
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/// spillVirtReg - Do the actual work of spilling.
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void RAFast::spillVirtReg(MachineBasicBlock::iterator MI,
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LiveRegMap::iterator lri, bool isKill) {
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LiveRegMap::iterator lri) {
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LiveReg &LR = lri->second;
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assert(PhysRegState[LR.PhysReg] == lri->first && "Broken RegState mapping");
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// If this physreg is used by the instruction, we want to kill it on the
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// instruction, not on the spill.
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bool spillKill = isKill && LR.LastUse != MI;
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if (LR.Dirty) {
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// If this physreg is used by the instruction, we want to kill it on the
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// instruction, not on the spill.
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bool spillKill = LR.LastUse != MI;
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LR.Dirty = false;
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DEBUG(dbgs() << "Spilling %reg" << lri->first
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<< " in " << TRI->getName(LR.PhysReg));
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@ -260,26 +255,18 @@ void RAFast::spillVirtReg(MachineBasicBlock::iterator MI,
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if (spillKill)
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LR.LastUse = 0; // Don't kill register again
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else if (!isKill) {
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MachineInstr *Spill = llvm::prior(MI);
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LR.LastUse = Spill;
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LR.LastOpNum = Spill->findRegisterUseOperandIdx(LR.PhysReg);
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}
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}
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if (isKill)
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killVirtReg(lri);
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killVirtReg(lri);
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}
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/// spillAll - Spill all dirty virtregs without killing them.
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void RAFast::spillAll(MachineInstr *MI) {
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SmallVector<unsigned, 16> Dirty;
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isBulkSpilling = true;
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for (LiveRegMap::iterator i = LiveVirtRegs.begin(),
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e = LiveVirtRegs.end(); i != e; ++i)
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if (i->second.Dirty)
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Dirty.push_back(i->first);
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for (unsigned i = 0, e = Dirty.size(); i != e; ++i)
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spillVirtReg(MI, Dirty[i], false);
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spillVirtReg(MI, i);
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LiveVirtRegs.clear();
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isBulkSpilling = false;
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}
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/// usePhysReg - Handle the direct use of a physical register.
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@ -352,7 +339,7 @@ void RAFast::definePhysReg(MachineInstr *MI, unsigned PhysReg,
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case regDisabled:
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break;
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default:
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spillVirtReg(MI, VirtReg, true);
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spillVirtReg(MI, VirtReg);
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// Fall through.
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case regFree:
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case regReserved:
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@ -369,7 +356,7 @@ void RAFast::definePhysReg(MachineInstr *MI, unsigned PhysReg,
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case regDisabled:
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break;
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default:
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spillVirtReg(MI, VirtReg, true);
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spillVirtReg(MI, VirtReg);
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// Fall through.
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case regFree:
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case regReserved:
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@ -435,7 +422,7 @@ void RAFast::allocVirtReg(MachineInstr *MI, LiveRegEntry &LRE, unsigned Hint) {
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case regReserved:
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break;
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default:
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spillVirtReg(MI, PhysRegState[Hint], true);
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spillVirtReg(MI, PhysRegState[Hint]);
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// Fall through.
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case regFree:
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return assignVirtToPhysReg(LRE, Hint);
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@ -512,7 +499,7 @@ void RAFast::allocVirtReg(MachineInstr *MI, LiveRegEntry &LRE, unsigned Hint) {
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// BestCost is 0 when all aliases are already disabled.
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if (BestCost) {
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if (PhysRegState[BestReg] != regDisabled)
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spillVirtReg(MI, PhysRegState[BestReg], true);
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spillVirtReg(MI, PhysRegState[BestReg]);
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else {
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// Make sure all aliases are disabled.
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for (const unsigned *AS = TRI->getAliasSet(BestReg);
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@ -524,7 +511,7 @@ void RAFast::allocVirtReg(MachineInstr *MI, LiveRegEntry &LRE, unsigned Hint) {
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PhysRegState[Alias] = regDisabled;
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break;
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default:
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spillVirtReg(MI, PhysRegState[Alias], true);
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spillVirtReg(MI, PhysRegState[Alias]);
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PhysRegState[Alias] = regDisabled;
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break;
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}
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@ -613,7 +600,6 @@ void RAFast::setPhysReg(MachineOperand &MO, unsigned PhysReg) {
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void RAFast::AllocateBasicBlock() {
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DEBUG(dbgs() << "\nAllocating " << *MBB);
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atEndOfBlock = false;
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PhysRegState.assign(TRI->getNumRegs(), regDisabled);
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assert(LiveVirtRegs.empty() && "Mapping not cleared form last block?");
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@ -794,25 +780,11 @@ void RAFast::AllocateBasicBlock() {
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}
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// Spill all physical registers holding virtual registers now.
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atEndOfBlock = true;
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MachineBasicBlock::iterator MI = MBB->getFirstTerminator();
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if (MI != MBB->end() && MI->getDesc().isReturn()) {
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// This is a return block, kill all virtual registers.
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DEBUG(dbgs() << "Killing live registers at end of return block.\n");
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for (LiveRegMap::iterator i = LiveVirtRegs.begin(), e = LiveVirtRegs.end();
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i != e; ++i)
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killVirtReg(i);
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} else {
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// This is a normal block, spill any dirty virtregs.
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DEBUG(dbgs() << "Spilling live registers at end of block.\n");
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for (LiveRegMap::iterator i = LiveVirtRegs.begin(), e = LiveVirtRegs.end();
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i != e; ++i)
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spillVirtReg(MI, i, true);
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}
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LiveVirtRegs.clear();
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DEBUG(dbgs() << "Spilling live registers at end of block.\n");
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spillAll(MBB->getFirstTerminator());
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// Erase all the coalesced copies. We are delaying it until now because
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// LiveVirtsRegs might refer to the instrs.
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// LiveVirtRegs might refer to the instrs.
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for (unsigned i = 0, e = Coalesced.size(); i != e; ++i)
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MBB->erase(Coalesced[i]);
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NumCopies += Coalesced.size();
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