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A addressing mode folding enhancement:

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Fold c2 in (x << c1) | c2 where (c2 < c1)
e.g.
int test(int x) {
  return (x << 3) + 7;
}

This can be codegen'd as:
leal 7(,%eax,8), %eax


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28550 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2006-05-30 06:59:36 +00:00
parent dc7dd9719d
commit e6ad27e917
2 changed files with 25 additions and 1 deletions
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24
lib/Target/X86/X86ISelDAGToDAG.cpp
View File

@ -392,6 +392,30 @@ bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM,
}
break;
}
case ISD::OR: {
if (!Available) {
X86ISelAddressMode Backup = AM;
// Look for (x << c1) | c2 where (c2 < c1)
ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(0));
if (CN && !MatchAddress(N.Val->getOperand(1), AM, false)) {
if (AM.GV == NULL && AM.Disp == 0 && CN->getValue() < AM.Scale) {
AM.Disp = CN->getValue();
return false;
}
}
AM = Backup;
CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1));
if (CN && !MatchAddress(N.Val->getOperand(0), AM, false)) {
if (AM.GV == NULL && AM.Disp == 0 && CN->getValue() < AM.Scale) {
AM.Disp = CN->getValue();
return false;
}
}
AM = Backup;
}
break;
}
}
// Is the base register already occupied?

2
lib/Target/X86/X86InstrInfo.td
View File

@ -133,7 +133,7 @@ def brtarget : Operand<OtherVT>;
// Define X86 specific addressing mode.
def addr : ComplexPattern<iPTR, 4, "SelectAddr", []>;
def leaaddr : ComplexPattern<iPTR, 4, "SelectLEAAddr",
[add, mul, shl, frameindex]>;
[add, mul, shl, or, frameindex]>;
//===----------------------------------------------------------------------===//
// X86 Instruction Format Definitions.