From e6d04f1a99f522be95ea45c4acb614f7e366d0d7 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Wed, 18 Feb 2004 16:43:51 +0000 Subject: [PATCH] Eliminate operator[] is deprecated warnings git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11578 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/InstrSched/SchedGraph.cpp | 37 +++++++++++--------- lib/Target/SparcV9/InstrSched/SchedGraph.cpp | 37 +++++++++++--------- 2 files changed, 42 insertions(+), 32 deletions(-) diff --git a/lib/CodeGen/InstrSched/SchedGraph.cpp b/lib/CodeGen/InstrSched/SchedGraph.cpp index 0547159e722..379fbfe8a7c 100644 --- a/lib/CodeGen/InstrSched/SchedGraph.cpp +++ b/lib/CodeGen/InstrSched/SchedGraph.cpp @@ -53,9 +53,12 @@ struct ValueToDefVecMap: public hash_map { SchedGraphNode::SchedGraphNode(unsigned NID, MachineBasicBlock *mbb, int indexInBB, const TargetMachine& Target) - : SchedGraphNodeCommon(NID,indexInBB), MBB(mbb), - MI(mbb ? &(*mbb)[indexInBB] : (MachineInstr*)0) { - if (MI) { + : SchedGraphNodeCommon(NID,indexInBB), MBB(mbb), MI(0) { + if (mbb) { + MachineBasicBlock::iterator I = MBB->begin(); + std::advance(I, indexInBB); + MI = I; + MachineOpCode mopCode = MI->getOpcode(); latency = Target.getInstrInfo().hasResultInterlock(mopCode) ? Target.getInstrInfo().minLatency(mopCode) @@ -183,11 +186,11 @@ void SchedGraph::addCDEdges(const TerminatorInst* term, // Now add CD edges to the first branch instruction in the sequence from // all preceding instructions in the basic block. Use 0 latency again. // - for (unsigned i=0, N=MBB.size(); i < N; i++) { - if (&MBB[i] == termMvec[first]) // reached the first branch + for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){ + if (&*I == termMvec[first]) // reached the first branch break; - SchedGraphNode* fromNode = this->getGraphNodeForInstr(&MBB[i]); + SchedGraphNode* fromNode = getGraphNodeForInstr(I); if (fromNode == NULL) continue; // dummy instruction, e.g., PHI @@ -199,11 +202,11 @@ void SchedGraph::addCDEdges(const TerminatorInst* term, // the terminator) that also have delay slots, add an outgoing edge // from the instruction to the instructions in the delay slots. // - unsigned d = mii.getNumDelaySlots(MBB[i].getOpcode()); - assert(i+d < N && "Insufficient delay slots for instruction?"); - - for (unsigned j=1; j <= d; j++) { - SchedGraphNode* toNode = this->getGraphNodeForInstr(&MBB[i+j]); + unsigned d = mii.getNumDelaySlots(I->getOpcode()); + + MachineBasicBlock::iterator J = I; ++J; + for (unsigned j=1; j <= d; j++, ++J) { + SchedGraphNode* toNode = this->getGraphNodeForInstr(J); assert(toNode && "No node for machine instr in delay slot?"); (void) new SchedGraphEdge(fromNode, toNode, SchedGraphEdge::CtrlDep, @@ -554,10 +557,12 @@ void SchedGraph::buildNodesForBB(const TargetMachine& target, // Build graph nodes for each VM instruction and gather def/use info. // Do both those together in a single pass over all machine instructions. - for (unsigned i=0; i < MBB.size(); i++) - if (!mii.isDummyPhiInstr(MBB[i].getOpcode())) { + unsigned i = 0; + for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; + ++I, ++i) + if (!mii.isDummyPhiInstr(I->getOpcode())) { SchedGraphNode* node = new SchedGraphNode(getNumNodes(), &MBB, i, target); - noteGraphNodeForInstr(&MBB[i], node); + noteGraphNodeForInstr(I, node); // Remember all register references and value defs findDefUseInfoAtInstr(target, node, memNodeVec, callDepNodeVec, @@ -632,8 +637,8 @@ void SchedGraph::buildGraph(const TargetMachine& target) { this->addCallDepEdges(callDepNodeVec, target); // Then add incoming def-use (SSA) edges for each machine instruction. - for (unsigned i=0, N=MBB.size(); i < N; i++) - addEdgesForInstruction(MBB[i], valueToDefVecMap, target); + for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I) + addEdgesForInstruction(*I, valueToDefVecMap, target); // Then add edges for dependences on machine registers this->addMachineRegEdges(regToRefVecMap, target); diff --git a/lib/Target/SparcV9/InstrSched/SchedGraph.cpp b/lib/Target/SparcV9/InstrSched/SchedGraph.cpp index 0547159e722..379fbfe8a7c 100644 --- a/lib/Target/SparcV9/InstrSched/SchedGraph.cpp +++ b/lib/Target/SparcV9/InstrSched/SchedGraph.cpp @@ -53,9 +53,12 @@ struct ValueToDefVecMap: public hash_map { SchedGraphNode::SchedGraphNode(unsigned NID, MachineBasicBlock *mbb, int indexInBB, const TargetMachine& Target) - : SchedGraphNodeCommon(NID,indexInBB), MBB(mbb), - MI(mbb ? &(*mbb)[indexInBB] : (MachineInstr*)0) { - if (MI) { + : SchedGraphNodeCommon(NID,indexInBB), MBB(mbb), MI(0) { + if (mbb) { + MachineBasicBlock::iterator I = MBB->begin(); + std::advance(I, indexInBB); + MI = I; + MachineOpCode mopCode = MI->getOpcode(); latency = Target.getInstrInfo().hasResultInterlock(mopCode) ? Target.getInstrInfo().minLatency(mopCode) @@ -183,11 +186,11 @@ void SchedGraph::addCDEdges(const TerminatorInst* term, // Now add CD edges to the first branch instruction in the sequence from // all preceding instructions in the basic block. Use 0 latency again. // - for (unsigned i=0, N=MBB.size(); i < N; i++) { - if (&MBB[i] == termMvec[first]) // reached the first branch + for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){ + if (&*I == termMvec[first]) // reached the first branch break; - SchedGraphNode* fromNode = this->getGraphNodeForInstr(&MBB[i]); + SchedGraphNode* fromNode = getGraphNodeForInstr(I); if (fromNode == NULL) continue; // dummy instruction, e.g., PHI @@ -199,11 +202,11 @@ void SchedGraph::addCDEdges(const TerminatorInst* term, // the terminator) that also have delay slots, add an outgoing edge // from the instruction to the instructions in the delay slots. // - unsigned d = mii.getNumDelaySlots(MBB[i].getOpcode()); - assert(i+d < N && "Insufficient delay slots for instruction?"); - - for (unsigned j=1; j <= d; j++) { - SchedGraphNode* toNode = this->getGraphNodeForInstr(&MBB[i+j]); + unsigned d = mii.getNumDelaySlots(I->getOpcode()); + + MachineBasicBlock::iterator J = I; ++J; + for (unsigned j=1; j <= d; j++, ++J) { + SchedGraphNode* toNode = this->getGraphNodeForInstr(J); assert(toNode && "No node for machine instr in delay slot?"); (void) new SchedGraphEdge(fromNode, toNode, SchedGraphEdge::CtrlDep, @@ -554,10 +557,12 @@ void SchedGraph::buildNodesForBB(const TargetMachine& target, // Build graph nodes for each VM instruction and gather def/use info. // Do both those together in a single pass over all machine instructions. - for (unsigned i=0; i < MBB.size(); i++) - if (!mii.isDummyPhiInstr(MBB[i].getOpcode())) { + unsigned i = 0; + for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; + ++I, ++i) + if (!mii.isDummyPhiInstr(I->getOpcode())) { SchedGraphNode* node = new SchedGraphNode(getNumNodes(), &MBB, i, target); - noteGraphNodeForInstr(&MBB[i], node); + noteGraphNodeForInstr(I, node); // Remember all register references and value defs findDefUseInfoAtInstr(target, node, memNodeVec, callDepNodeVec, @@ -632,8 +637,8 @@ void SchedGraph::buildGraph(const TargetMachine& target) { this->addCallDepEdges(callDepNodeVec, target); // Then add incoming def-use (SSA) edges for each machine instruction. - for (unsigned i=0, N=MBB.size(); i < N; i++) - addEdgesForInstruction(MBB[i], valueToDefVecMap, target); + for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I) + addEdgesForInstruction(*I, valueToDefVecMap, target); // Then add edges for dependences on machine registers this->addMachineRegEdges(regToRefVecMap, target);