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Remove unused argument to CreateTargetScheduleState and change

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the TargetMachine to a TargetSubtargetInfo since everything
we wanted is off of that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219382 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2014-10-09 01:59:35 +00:00
parent 939dd38a09
commit e6d97094b7
8 changed files with 18 additions and 22 deletions
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4
include/llvm/Target/TargetInstrInfo.h
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@ -1185,8 +1185,8 @@ public:
const TargetRegisterInfo *TRI) const {}
/// Create machine specific model for scheduling.
virtual DFAPacketizer*
CreateTargetScheduleState(const TargetMachine*, const ScheduleDAG*) const {
virtual DFAPacketizer *
CreateTargetScheduleState(const TargetSubtargetInfo &) const {
return nullptr;
}

2
lib/CodeGen/DFAPacketizer.cpp
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@ -128,7 +128,7 @@ VLIWPacketizerList::VLIWPacketizerList(MachineFunction &MF,
MachineLoopInfo &MLI, bool IsPostRA)
: TM(MF.getTarget()), MF(MF) {
TII = TM.getSubtargetImpl()->getInstrInfo();
ResourceTracker = TII->CreateTargetScheduleState(&TM, nullptr);
ResourceTracker = TII->CreateTargetScheduleState(MF.getSubtarget());
VLIWScheduler = new DefaultVLIWScheduler(MF, MLI, IsPostRA);
}

2
lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp
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@ -47,7 +47,7 @@ ResourcePriorityQueue::ResourcePriorityQueue(SelectionDAGISel *IS)
TRI = STI.getRegisterInfo();
TLI = IS->TLI;
TII = STI.getInstrInfo();
ResourcesModel = TII->CreateTargetScheduleState(&IS->MF->getTarget(), nullptr);
ResourcesModel = TII->CreateTargetScheduleState(STI);
// This hard requirement could be relaxed, but for now
// do not let it procede.
assert(ResourcesModel && "Unimplemented CreateTargetScheduleState.");

10
lib/Target/Hexagon/HexagonInstrInfo.cpp
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@ -1636,12 +1636,10 @@ void HexagonInstrInfo::immediateExtend(MachineInstr *MI) const {
MO.addTargetFlag(HexagonII::HMOTF_ConstExtended);
}
DFAPacketizer *HexagonInstrInfo::
CreateTargetScheduleState(const TargetMachine *TM,
const ScheduleDAG *DAG) const {
const InstrItineraryData *II =
TM->getSubtargetImpl()->getInstrItineraryData();
return TM->getSubtarget<HexagonGenSubtargetInfo>().createDFAPacketizer(II);
DFAPacketizer *HexagonInstrInfo::CreateTargetScheduleState(
const TargetSubtargetInfo &STI) const {
const InstrItineraryData *II = STI.getInstrItineraryData();
return static_cast<const HexagonSubtarget &>(STI).createDFAPacketizer(II);
}
bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr *MI,

5
lib/Target/Hexagon/HexagonInstrInfo.h
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@ -148,9 +148,8 @@ public:
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
const BranchProbability &Probability) const override;
DFAPacketizer*
CreateTargetScheduleState(const TargetMachine *TM,
const ScheduleDAG *DAG) const override;
DFAPacketizer *
CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override;
bool isSchedulingBoundary(const MachineInstr *MI,
const MachineBasicBlock *MBB,

4
lib/Target/Hexagon/HexagonMachineScheduler.h
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@ -57,8 +57,8 @@ public:
VLIWResourceModel(const TargetMachine &TM, const TargetSchedModel *SM) :
SchedModel(SM), TotalPackets(0) {
ResourcesModel =
TM.getSubtargetImpl()->getInstrInfo()->CreateTargetScheduleState(&TM,
nullptr);
TM.getSubtargetImpl()->getInstrInfo()->CreateTargetScheduleState(
*TM.getSubtargetImpl());
// This hard requirement could be relaxed,
// but for now do not let it proceed.

9
lib/Target/R600/R600InstrInfo.cpp
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@ -654,11 +654,10 @@ R600InstrInfo::fitsConstReadLimitations(const std::vector<MachineInstr *> &MIs)
return fitsConstReadLimitations(Consts);
}
DFAPacketizer *R600InstrInfo::CreateTargetScheduleState(const TargetMachine *TM,
const ScheduleDAG *DAG) const {
const InstrItineraryData *II =
TM->getSubtargetImpl()->getInstrItineraryData();
return TM->getSubtarget<AMDGPUSubtarget>().createDFAPacketizer(II);
DFAPacketizer *
R600InstrInfo::CreateTargetScheduleState(const TargetSubtargetInfo &STI) const {
const InstrItineraryData *II = STI.getInstrItineraryData();
return static_cast<const AMDGPUSubtarget &>(STI).createDFAPacketizer(II);
}
static bool

4
lib/Target/R600/R600InstrInfo.h
View File

@ -154,8 +154,8 @@ namespace llvm {
bool isMov(unsigned Opcode) const override;
DFAPacketizer *CreateTargetScheduleState(const TargetMachine *TM,
const ScheduleDAG *DAG) const override;
DFAPacketizer *
CreateTargetScheduleState(const TargetSubtargetInfo &) const override;
bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;