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Remove liveout lists from MachineRegisterInfo.

Browse Source 
All targets are now adding return value registers as implicit uses on
return instructions, and there is no longer a need for the live out
lists.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174417 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2013-02-05 18:21:56 +00:00
parent b45e4deb10
commit e6dc59891f
4 changed files with 6 additions and 27 deletions
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15
include/llvm/CodeGen/MachineRegisterInfo.h
View File

@ -99,13 +99,11 @@ class MachineRegisterInfo {
/// started.
BitVector ReservedRegs;
/// LiveIns/LiveOuts - Keep track of the physical registers that are
/// livein/liveout of the function. Live in values are typically arguments in
/// registers, live out values are typically return values in registers.
/// LiveIn values are allowed to have virtual registers associated with them,
/// stored in the second element.
/// Keep track of the physical registers that are live in to the function.
/// Live in values are typically arguments in registers, live out values are
/// typically return values in registers. LiveIn values are allowed to have
/// virtual registers associated with them, stored in the second element.
std::vector<std::pair<unsigned, unsigned> > LiveIns;
std::vector<unsigned> LiveOuts;
MachineRegisterInfo(const MachineRegisterInfo&) LLVM_DELETED_FUNCTION;
void operator=(const MachineRegisterInfo&) LLVM_DELETED_FUNCTION;
@ -468,7 +466,6 @@ public:
void addLiveIn(unsigned Reg, unsigned vreg = 0) {
LiveIns.push_back(std::make_pair(Reg, vreg));
}
void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); }
// Iteration support for live in/out sets. These sets are kept in sorted
// order by their register number.
@ -478,12 +475,8 @@ public:
livein_iterator livein_begin() const { return LiveIns.begin(); }
livein_iterator livein_end() const { return LiveIns.end(); }
bool livein_empty() const { return LiveIns.empty(); }
liveout_iterator liveout_begin() const { return LiveOuts.begin(); }
liveout_iterator liveout_end() const { return LiveOuts.end(); }
bool liveout_empty() const { return LiveOuts.empty(); }
bool isLiveIn(unsigned Reg) const;
bool isLiveOut(unsigned Reg) const;
/// getLiveInPhysReg - If VReg is a live-in virtual register, return the
/// corresponding live-in physical register.

7
lib/CodeGen/MachineFunction.cpp
View File

@ -346,13 +346,6 @@ void MachineFunction::print(raw_ostream &OS, SlotIndexes *Indexes) const {
}
OS << '\n';
}
if (RegInfo && !RegInfo->liveout_empty()) {
OS << "Function Live Outs:";
for (MachineRegisterInfo::liveout_iterator
I = RegInfo->liveout_begin(), E = RegInfo->liveout_end(); I != E; ++I)
OS << ' ' << PrintReg(*I, TRI);
OS << '\n';
}
for (const_iterator BB = begin(), E = end(); BB != E; ++BB) {
OS << '\n';

4
lib/CodeGen/MachineInstr.cpp
View File

@ -1515,12 +1515,12 @@ void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM,
unsigned Reg = MO.getReg();
if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
const MachineRegisterInfo &MRI = MF->getRegInfo();
if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) {
if (MRI.use_empty(Reg)) {
bool HasAliasLive = false;
for (MCRegAliasIterator AI(Reg, TM->getRegisterInfo(), true);
AI.isValid(); ++AI) {
unsigned AliasReg = *AI;
if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) {
if (!MRI.use_empty(AliasReg)) {
HasAliasLive = true;
break;
}

7
lib/CodeGen/MachineRegisterInfo.cpp
View File

@ -283,13 +283,6 @@ bool MachineRegisterInfo::isLiveIn(unsigned Reg) const {
return false;
}
bool MachineRegisterInfo::isLiveOut(unsigned Reg) const {
for (liveout_iterator I = liveout_begin(), E = liveout_end(); I != E; ++I)
if (*I == Reg)
return true;
return false;
}
/// getLiveInPhysReg - If VReg is a live-in virtual register, return the
/// corresponding live-in physical register.
unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const {