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[x86] Infer disassembler mode from SubtargetInfo feature bits

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Aside from cleaning up the code, this also adds support for the -code16
environment and actually enables the MODE_16BIT mode that was previously
not accessible.

There is no point adding any testing for 16-bit yet though; basically
nothing will work because we aren't handling the OpSize prefix correctly
for 16-bit mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199649 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
David Woodhouse 2014-01-20 12:02:31 +00:00
parent 70ece0ada7
commit e6f5bb99fc
2 changed files with 24 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
lib/Target/X86/Disassembler/X86Disassembler.cpp
View File

@ -31,6 +31,8 @@
#include "X86GenRegisterInfo.inc" #include "X86GenRegisterInfo.inc"
#define GET_INSTRINFO_ENUM #define GET_INSTRINFO_ENUM
#include "X86GenInstrInfo.inc" #include "X86GenInstrInfo.inc"
#define GET_SUBTARGETINFO_ENUM
#include "X86GenSubtargetInfo.inc"
using namespace llvm; using namespace llvm;
using namespace llvm::X86Disassembler; using namespace llvm::X86Disassembler;
@ -73,9 +75,23 @@ static bool translateInstruction(MCInst &target,
const MCDisassembler *Dis); const MCDisassembler *Dis);
X86GenericDisassembler::X86GenericDisassembler(const MCSubtargetInfo &STI, X86GenericDisassembler::X86GenericDisassembler(const MCSubtargetInfo &STI,
DisassemblerMode mode,
const MCInstrInfo *MII) const MCInstrInfo *MII)
: MCDisassembler(STI), MII(MII), fMode(mode) {} : MCDisassembler(STI), MII(MII) {
switch (STI.getFeatureBits() &
(X86::Mode16Bit | X86::Mode32Bit | X86::Mode64Bit)) {
case X86::Mode16Bit:
fMode = MODE_16BIT;
break;
case X86::Mode32Bit:
fMode = MODE_32BIT;
break;
case X86::Mode64Bit:
fMode = MODE_64BIT;
break;
default:
llvm_unreachable("Invalid CPU mode");
}
}
X86GenericDisassembler::~X86GenericDisassembler() { X86GenericDisassembler::~X86GenericDisassembler() {
delete MII; delete MII;
@ -737,22 +753,16 @@ static bool translateInstruction(MCInst &mcInst,
return false; return false;
} }
static MCDisassembler *createX86_32Disassembler(const Target &T, static MCDisassembler *createX86Disassembler(const Target &T,
const MCSubtargetInfo &STI) { const MCSubtargetInfo &STI) {
return new X86Disassembler::X86GenericDisassembler(STI, MODE_32BIT, return new X86Disassembler::X86GenericDisassembler(STI,
T.createMCInstrInfo());
}
static MCDisassembler *createX86_64Disassembler(const Target &T,
const MCSubtargetInfo &STI) {
return new X86Disassembler::X86GenericDisassembler(STI, MODE_64BIT,
T.createMCInstrInfo()); T.createMCInstrInfo());
} }
extern "C" void LLVMInitializeX86Disassembler() { extern "C" void LLVMInitializeX86Disassembler() {
// Register the disassembler. // Register the disassembler.
TargetRegistry::RegisterMCDisassembler(TheX86_32Target, TargetRegistry::RegisterMCDisassembler(TheX86_32Target,
createX86_32Disassembler); createX86Disassembler);
TargetRegistry::RegisterMCDisassembler(TheX86_64Target, TargetRegistry::RegisterMCDisassembler(TheX86_64Target,
createX86_64Disassembler); createX86Disassembler);
} }

4
lib/Target/X86/Disassembler/X86Disassembler.h
View File

@ -105,9 +105,7 @@ class X86GenericDisassembler : public MCDisassembler {
public: public:
/// Constructor - Initializes the disassembler. /// Constructor - Initializes the disassembler.
/// ///
/// @param mode - The X86 architecture mode to decode for. X86GenericDisassembler(const MCSubtargetInfo &STI, const MCInstrInfo *MII);
X86GenericDisassembler(const MCSubtargetInfo &STI, DisassemblerMode mode,
const MCInstrInfo *MII);
private: private:
~X86GenericDisassembler(); ~X86GenericDisassembler();
public: public: