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https://github.com/c64scene-ar/llvm-6502.git
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ARMv8 IfConversion must skip narrow instructions that a) define CPSR and b) wouldn't affect CPSR in an IT block
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202257 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Artyom Skrobov
parent
3d0b469690
commit
e708238373
@ -535,6 +535,20 @@ bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
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return true;
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}
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template<> bool IsCPSRDead<MachineInstr>(MachineInstr* MI) {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg() || MO.isUndef() || MO.isUse())
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continue;
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if (MO.getReg() != ARM::CPSR)
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continue;
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if (!MO.isDead())
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return false;
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}
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// all definitions of CPSR are dead
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return true;
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}
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/// FIXME: Works around a gcc miscompilation with -fstrict-aliasing.
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LLVM_ATTRIBUTE_NOINLINE
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static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
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@ -16,6 +16,9 @@
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#include "ARM.h"
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template<typename InstrType> // could be MachineInstr or MCInst
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bool IsCPSRDead(InstrType *Instr);
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namespace llvm {
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template<typename InstrType> // could be MachineInstr or MCInst
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@ -26,25 +29,12 @@ inline bool isV8EligibleForIT(InstrType *Instr) {
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case ARM::tADC:
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case ARM::tADDi3:
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case ARM::tADDi8:
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case ARM::tADDrSPi:
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case ARM::tADDrr:
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case ARM::tAND:
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case ARM::tASRri:
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case ARM::tASRrr:
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case ARM::tBIC:
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case ARM::tCMNz:
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case ARM::tCMPi8:
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case ARM::tCMPr:
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case ARM::tEOR:
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case ARM::tLDRBi:
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case ARM::tLDRBr:
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case ARM::tLDRHi:
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case ARM::tLDRHr:
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case ARM::tLDRSB:
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case ARM::tLDRSH:
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case ARM::tLDRi:
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case ARM::tLDRr:
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case ARM::tLDRspi:
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case ARM::tLSLri:
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case ARM::tLSLrr:
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case ARM::tLSRri:
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@ -56,6 +46,24 @@ inline bool isV8EligibleForIT(InstrType *Instr) {
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case ARM::tROR:
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case ARM::tRSB:
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case ARM::tSBC:
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case ARM::tSUBi3:
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case ARM::tSUBi8:
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case ARM::tSUBrr:
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// Outside of an IT block, these set CPSR.
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return IsCPSRDead(Instr);
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case ARM::tADDrSPi:
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case ARM::tCMNz:
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case ARM::tCMPi8:
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case ARM::tCMPr:
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case ARM::tLDRBi:
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case ARM::tLDRBr:
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case ARM::tLDRHi:
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case ARM::tLDRHr:
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case ARM::tLDRSB:
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case ARM::tLDRSH:
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case ARM::tLDRi:
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case ARM::tLDRr:
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case ARM::tLDRspi:
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case ARM::tSTRBi:
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case ARM::tSTRBr:
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case ARM::tSTRHi:
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@ -63,9 +71,6 @@ inline bool isV8EligibleForIT(InstrType *Instr) {
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case ARM::tSTRi:
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case ARM::tSTRr:
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case ARM::tSTRspi:
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case ARM::tSUBi3:
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case ARM::tSUBi8:
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case ARM::tSUBrr:
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case ARM::tTST:
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return true;
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// there are some "conditionally deprecated" opcodes
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@ -7850,6 +7850,10 @@ unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
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return Match_Success;
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}
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template<> inline bool IsCPSRDead<MCInst>(MCInst* Instr) {
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return true; // In an assembly source, no need to second-guess
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}
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static const char *getSubtargetFeatureName(unsigned Val);
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bool ARMAsmParser::
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MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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100
test/CodeGen/Thumb2/v8_IT_6.ll
Normal file
100
test/CodeGen/Thumb2/v8_IT_6.ll
Normal file
@ -0,0 +1,100 @@
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; RUN: llc < %s -mtriple=thumbv8 -show-mc-encoding | FileCheck %s
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; CHECK-NOT: orrsne r0, r1 @ encoding: [0x08,0x43]
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; Narrow tORR cannot be predicated and set CPSR at the same time!
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declare void @f(i32)
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define void @initCloneLookups() #1 {
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entry:
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br label %for.cond1.preheader
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for.cond1.preheader: ; preds = %for.inc24, %entry
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%cmp108 = phi i1 [ true, %entry ], [ %cmp, %for.inc24 ]
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%y.0105 = phi i32 [ 1, %entry ], [ %inc25, %for.inc24 ]
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%notlhs = icmp slt i32 %y.0105, 6
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%notlhs69 = icmp sgt i32 %y.0105, 4
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%sub = add nsw i32 %y.0105, -1
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%cmp1.i = icmp sgt i32 %sub, 5
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%cmp1.i54 = icmp sgt i32 %y.0105, 5
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br i1 %cmp108, label %if.then.us, label %for.cond1.preheader.for.cond1.preheader.split_crit_edge
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for.cond1.preheader.for.cond1.preheader.split_crit_edge: ; preds = %for.cond1.preheader
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br i1 %notlhs, label %for.inc.us101, label %for.inc
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if.then.us: ; preds = %for.cond1.preheader, %for.inc.us
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%x.071.us = phi i32 [ %inc.us.pre-phi, %for.inc.us ], [ 1, %for.cond1.preheader ]
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%notrhs.us = icmp sge i32 %x.071.us, %y.0105
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%or.cond44.not.us = or i1 %notrhs.us, %notlhs
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%notrhs70.us = icmp sle i32 %x.071.us, %y.0105
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%tobool.us = or i1 %notrhs70.us, %notlhs69
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%or.cond66.us = and i1 %or.cond44.not.us, %tobool.us
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br i1 %or.cond66.us, label %getHexxagonIndex.exit52.us, label %if.then.us.for.inc.us_crit_edge
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if.then.us.for.inc.us_crit_edge: ; preds = %if.then.us
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%inc.us.pre = add nsw i32 %x.071.us, 1
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br label %for.inc.us
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getHexxagonIndex.exit52.us: ; preds = %if.then.us
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%cmp3.i.us = icmp slt i32 %x.071.us, 5
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%or.cond.i.us = and i1 %cmp1.i, %cmp3.i.us
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%..i.us = sext i1 %or.cond.i.us to i32
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tail call void @f(i32 %..i.us) #3
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%add.us = add nsw i32 %x.071.us, 1
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%cmp3.i55.us = icmp slt i32 %add.us, 5
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%or.cond.i56.us = and i1 %cmp1.i54, %cmp3.i55.us
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%..i57.us = sext i1 %or.cond.i56.us to i32
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tail call void @f(i32 %..i57.us) #3
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%or.cond.i48.us = and i1 %notlhs69, %cmp3.i55.us
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%..i49.us = sext i1 %or.cond.i48.us to i32
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tail call void @f(i32 %..i49.us) #3
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br label %for.inc.us
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for.inc.us: ; preds = %if.then.us.for.inc.us_crit_edge, %getHexxagonIndex.exit52.us
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%inc.us.pre-phi = phi i32 [ %inc.us.pre, %if.then.us.for.inc.us_crit_edge ], [ %add.us, %getHexxagonIndex.exit52.us ]
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%exitcond109 = icmp eq i32 %inc.us.pre-phi, 10
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br i1 %exitcond109, label %for.inc24, label %if.then.us
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for.inc.us101: ; preds = %for.cond1.preheader.for.cond1.preheader.split_crit_edge, %for.inc.us101
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%x.071.us74 = phi i32 [ %add.us89, %for.inc.us101 ], [ 1, %for.cond1.preheader.for.cond1.preheader.split_crit_edge ]
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%cmp3.i.us84 = icmp slt i32 %x.071.us74, 5
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%or.cond.i.us85 = and i1 %cmp1.i, %cmp3.i.us84
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%..i.us86 = sext i1 %or.cond.i.us85 to i32
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tail call void @f(i32 %..i.us86) #3
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%add.us89 = add nsw i32 %x.071.us74, 1
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%cmp3.i55.us93 = icmp slt i32 %add.us89, 5
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%or.cond.i56.us94 = and i1 %cmp1.i54, %cmp3.i55.us93
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%..i57.us95 = sext i1 %or.cond.i56.us94 to i32
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tail call void @f(i32 %..i57.us95) #3
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%or.cond.i48.us97 = and i1 %notlhs69, %cmp3.i55.us93
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%..i49.us98 = sext i1 %or.cond.i48.us97 to i32
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tail call void @f(i32 %..i49.us98) #3
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%exitcond110 = icmp eq i32 %add.us89, 10
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br i1 %exitcond110, label %for.inc24, label %for.inc.us101
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for.inc: ; preds = %for.cond1.preheader.for.cond1.preheader.split_crit_edge, %for.inc
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%x.071 = phi i32 [ %add, %for.inc ], [ 1, %for.cond1.preheader.for.cond1.preheader.split_crit_edge ]
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%cmp3.i = icmp slt i32 %x.071, 5
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%or.cond.i = and i1 %cmp1.i, %cmp3.i
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%..i = sext i1 %or.cond.i to i32
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tail call void @f(i32 %..i) #3
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%add = add nsw i32 %x.071, 1
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%cmp3.i55 = icmp slt i32 %add, 5
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%or.cond.i56 = and i1 %cmp1.i54, %cmp3.i55
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%..i57 = sext i1 %or.cond.i56 to i32
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tail call void @f(i32 %..i57) #3
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%or.cond.i48 = and i1 %notlhs69, %cmp3.i55
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%..i49 = sext i1 %or.cond.i48 to i32
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tail call void @f(i32 %..i49) #3
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%exitcond = icmp eq i32 %add, 10
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br i1 %exitcond, label %for.inc24, label %for.inc
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for.inc24: ; preds = %for.inc, %for.inc.us101, %for.inc.us
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%inc25 = add nsw i32 %y.0105, 1
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%cmp = icmp slt i32 %inc25, 10
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%exitcond111 = icmp eq i32 %inc25, 10
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br i1 %exitcond111, label %for.end26, label %for.cond1.preheader
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for.end26: ; preds = %for.inc24
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ret void
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}
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