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Add definitions of 64-bit instructions which move data between integer and

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floating pointer registers.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144016 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2011-11-07 21:32:58 +00:00
parent d8f9f34230
commit e7126ebd54
1 changed files with 8 additions and 0 deletions
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8
lib/Target/Mips/MipsInstrFPU.td
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@ -183,6 +183,14 @@ def MTC1 : FFRGPR<0x04, (outs FGR32:$fs), (ins CPURegs:$rt),
"mtc1\t$rt, $fs",
[(set FGR32:$fs, (bitconvert CPURegs:$rt))]>;
def DMFC1 : FFRGPR<0x01, (outs CPU64Regs:$rt), (ins FGR64:$fs),
"dmfc1\t$rt, $fs",
[(set CPU64Regs:$rt, (bitconvert FGR64:$fs))]>;
def DMTC1 : FFRGPR<0x05, (outs FGR64:$fs), (ins CPU64Regs:$rt),
"dmtc1\t$rt, $fs",
[(set FGR64:$fs, (bitconvert CPU64Regs:$rt))]>;
def FMOV_S : FFR1<0x6, 16, "mov", "s", FGR32, FGR32>;
def FMOV_D32 : FFR1<0x6, 17, "mov", "d", AFGR64, AFGR64>,
Requires<[NotFP64bit]>;