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More Neon clean-up: avoid the need for custom-lowering vld/st-lane intrinsics

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by creating TargetConstants during instruction selection instead of during
legalization.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84042 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson
2009-10-13 22:29:24 +00:00
parent cfe0724016
commit e72142aa5b
2 changed files with 24 additions and 90 deletions
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lib/Target/ARM/ARMISelLowering.cpp
-54
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@@ -392,8 +392,6 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
// We want to custom lower some of our intrinsics.
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
setOperationAction(ISD::SETCC, MVT::i32, Expand);
setOperationAction(ISD::SETCC, MVT::f32, Expand);
@@ -1369,56 +1367,6 @@ SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
}
static SDValue LowerNeonVLDLaneIntrinsic(SDValue Op, SelectionDAG &DAG,
unsigned NumVecs) {
// Change the lane number operand to be a TargetConstant; otherwise it
// will be legalized into a register.
SDNode *Node = Op.getNode();
ConstantSDNode *Lane = dyn_cast<ConstantSDNode>(Node->getOperand(NumVecs+3));
if (!Lane) {
assert(false && "vld lane number must be a constant");
return SDValue();
}
SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
Ops[NumVecs+3] = DAG.getTargetConstant(Lane->getZExtValue(), MVT::i32);
return DAG.UpdateNodeOperands(Op, &Ops[0], Ops.size());
}
static SDValue LowerNeonVSTLaneIntrinsic(SDValue Op, SelectionDAG &DAG,
unsigned NumVecs) {
// Change the lane number operand to be a TargetConstant; otherwise it
// will be legalized into a register.
SDNode *Node = Op.getNode();
ConstantSDNode *Lane = dyn_cast<ConstantSDNode>(Node->getOperand(NumVecs+3));
if (!Lane) {
assert(false && "vst lane number must be a constant");
return SDValue();
}
SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
Ops[NumVecs+3] = DAG.getTargetConstant(Lane->getZExtValue(), MVT::i32);
return DAG.UpdateNodeOperands(Op, &Ops[0], Ops.size());
}
SDValue
ARMTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) {
unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
switch (IntNo) {
case Intrinsic::arm_neon_vld2lane:
return LowerNeonVLDLaneIntrinsic(Op, DAG, 2);
case Intrinsic::arm_neon_vld3lane:
return LowerNeonVLDLaneIntrinsic(Op, DAG, 3);
case Intrinsic::arm_neon_vld4lane:
return LowerNeonVLDLaneIntrinsic(Op, DAG, 4);
case Intrinsic::arm_neon_vst2lane:
return LowerNeonVSTLaneIntrinsic(Op, DAG, 2);
case Intrinsic::arm_neon_vst3lane:
return LowerNeonVSTLaneIntrinsic(Op, DAG, 3);
case Intrinsic::arm_neon_vst4lane:
return LowerNeonVSTLaneIntrinsic(Op, DAG, 4);
default: return SDValue(); // Don't custom lower most intrinsics.
}
}
SDValue
ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
@@ -2802,8 +2750,6 @@ SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
case ISD::RETURNADDR: break;
case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
case ISD::INTRINSIC_VOID:
case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(Op.getNode(), DAG);
case ISD::SHL: