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Fix library visibility problems with VLIWPacketizer.

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The existing framework for postra scheduling is library local. We want to keep it that way. Soon we will have a more general MachineScheduler interface. At that time, various bits will be exposed to targets. In the meantime, the VLIWPacketizer wants to use ScheduleDAGInstrs directly, so it needs to wrapped in a PIMPL to avoid exposing it to the target interface.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150633 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick 2012-02-15 23:34:15 +00:00
parent 426f215732
commit e746186ed4
2 changed files with 22 additions and 9 deletions
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6
include/llvm/CodeGen/DFAPacketizer.h
View File

@ -36,7 +36,7 @@ class MachineInstr;
class MachineLoopInfo;
class MachineDominatorTree;
class InstrItineraryData;
class ScheduleDAGInstrs;
class VLIWPacketizerImpl;
class SUnit;
class DFAPacketizer {
@ -91,8 +91,8 @@ class VLIWPacketizerList {
const MachineFunction &MF;
const TargetInstrInfo *TII;
// The VLIW Scheduler.
ScheduleDAGInstrs *VLIWScheduler;
// Encapsulate data types not exposed to the target interface.
VLIWPacketizerImpl *Impl;
protected:
// Vector of instructions assigned to the current packet.

23
lib/CodeGen/DFAPacketizer.cpp
View File

@ -103,6 +103,9 @@ void DFAPacketizer::reserveResources(llvm::MachineInstr *MI) {
namespace {
// DefaultVLIWScheduler - This class extends ScheduleDAGInstrs and overrides
// Schedule method to build the dependence graph.
//
// ScheduleDAGInstrs has LLVM_LIBRARY_VISIBILITY so cannot be exposed to the
// VLIWPacketizerImpl interface, even as an undefined pointer.
class DefaultVLIWScheduler : public ScheduleDAGInstrs {
public:
DefaultVLIWScheduler(MachineFunction &MF, MachineLoopInfo &MLI,
@ -112,6 +115,17 @@ public:
};
}
namespace llvm {
// Wrapper for holding library-local data types.
class VLIWPacketizerImpl {
public:
DefaultVLIWScheduler DAGBuilder;
VLIWPacketizerImpl(MachineFunction &MF, MachineLoopInfo &MLI,
MachineDominatorTree &MDT, bool IsPostRA)
: DAGBuilder(MF, MLI, MDT, IsPostRA) {}
};
}
DefaultVLIWScheduler::DefaultVLIWScheduler(
MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
bool IsPostRA) :
@ -129,12 +143,12 @@ VLIWPacketizerList::VLIWPacketizerList(
bool IsPostRA) : TM(MF.getTarget()), MF(MF) {
TII = TM.getInstrInfo();
ResourceTracker = TII->CreateTargetScheduleState(&TM, 0);
VLIWScheduler = new DefaultVLIWScheduler(MF, MLI, MDT, IsPostRA);
Impl = new VLIWPacketizerImpl(MF, MLI, MDT, IsPostRA);
}
// VLIWPacketizerList Dtor
VLIWPacketizerList::~VLIWPacketizerList() {
delete VLIWScheduler;
delete Impl;
delete ResourceTracker;
}
@ -181,11 +195,10 @@ void VLIWPacketizerList::endPacket(MachineBasicBlock *MBB,
void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB,
MachineBasicBlock::iterator BeginItr,
MachineBasicBlock::iterator EndItr) {
assert(VLIWScheduler && "VLIW Scheduler is not initialized!");
VLIWScheduler->Run(MBB, BeginItr, EndItr, MBB->size());
Impl->DAGBuilder.Run(MBB, BeginItr, EndItr, MBB->size());
// Remember scheduling units.
SUnits = VLIWScheduler->SUnits;
SUnits = Impl->DAGBuilder.SUnits;
// Generate MI -> SU map.
std::map <MachineInstr*, SUnit*> MIToSUnit;