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Position Independent Code (PIC) support [1]
- Modified instruction format to handle pseudo instructions - Added LoadAddr SDNode to load symbols. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42778 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -42,6 +42,9 @@ class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
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let Itinerary = itin;
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}
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// Mips Pseudo Instructions Format
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class PseudoInstMips<dag outs, dag ins, string asmstr, list<dag> pattern>:
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MipsInst<outs, ins, asmstr, pattern, IIPseudo>;
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//===----------------------------------------------------------------------===//
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// Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
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@ -98,3 +101,4 @@ class FJ<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
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let Inst{25-0} = addr;
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}
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@ -24,7 +24,7 @@ def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, [SDNPHasChain,
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// Hi and Lo nodes are created to let easy manipulation of 16-bit when
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// handling 32-bit immediates. They are used on MipsISelLowering to
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// lower stuff like GlobalAddress, ExternalSymbol, ...
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// lower stuff like GlobalAddress, ExternalSymbol, ... on static model
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// This two nodes have nothing to do with Mips Registers Hi and Lo.
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def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp, [SDNPOutFlag]>;
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def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
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@ -34,6 +34,9 @@ def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
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def MipsAdd : SDNode<"MipsISD::Add", SDTIntBinOp, [SDNPCommutative,
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SDNPAssociative, SDNPOptInFlag]>;
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// Used to Load Addresses on PIC code.
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def MipsLoadAddr: SDNode<"MipsISD::LoadAddr", SDTIntUnaryOp>;
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// Return
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def SDT_MipsRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
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def MipsRet : SDNode<"MipsISD::Ret", SDT_MipsRet, [SDNPHasChain,
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@ -46,12 +49,22 @@ def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeq,
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def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeq,
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[SDNPHasChain, SDNPOutFlag]>;
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//===----------------------------------------------------------------------===//
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// Mips Instruction Predicate Definitions.
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//===----------------------------------------------------------------------===//
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def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
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//===----------------------------------------------------------------------===//
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// Mips Operand, Complex Patterns and Transformations Definitions.
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//===----------------------------------------------------------------------===//
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// Instruction operand types
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def brtarget : Operand<OtherVT>;
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def calltarget : Operand<i32>;
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def uimm16 : Operand<i32>;
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def simm16 : Operand<i32>;
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def shamt : Operand<i32>;
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def addrlabel : Operand<i32>;
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// Address operand
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def mem : Operand<i32> {
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@ -59,10 +72,6 @@ def mem : Operand<i32> {
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let MIOperandInfo = (ops simm16, CPURegs);
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}
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//===----------------------------------------------------------------------===//
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// Mips Patterns and Transformations
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//===----------------------------------------------------------------------===//
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// Transformation Function - get the lower 16 bits.
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def LO16 : SDNodeXForm<imm, [{
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return getI32Imm((unsigned)N->getValue() & 0xFFFF);
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@ -280,7 +289,7 @@ class JumpFR<bits<6> op, bits<6> func, string instr_asm>:
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let isCall=1, hasDelaySlot=1,
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// All calls clobber the non-callee saved registers...
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Defs = [AT, V0, V1, A0, A1, A2, A3, T0, T1, T2,
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T3, T4, T5, T6, T7, T8, T9, K0, K1, GP] in {
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T3, T4, T5, T6, T7, T8, T9, K0, K1] in {
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class JumpLink<bits<6> op, string instr_asm>:
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FJ< op,
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(outs),
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@ -343,22 +352,34 @@ class EffectiveAddress<string instr_asm> :
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// Pseudo instructions
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//===----------------------------------------------------------------------===//
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class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>:
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MipsInst<outs, ins, asmstr, pattern, IIPseudo>;
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// As stack alignment is always done with addiu, we need a 16-bit immediate
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let Defs = [SP], Uses = [SP] in {
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def ADJCALLSTACKDOWN : Pseudo<(outs), (ins uimm16:$amt),
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"!ADJCALLSTACKDOWN $amt",
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[(callseq_start imm:$amt)]>;
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def ADJCALLSTACKUP : Pseudo<(outs), (ins uimm16:$amt),
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"!ADJCALLSTACKUP $amt",
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[(callseq_end imm:$amt)]>;
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def ADJCALLSTACKDOWN : PseudoInstMips<(outs), (ins uimm16:$amt),
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"!ADJCALLSTACKDOWN $amt",
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[(callseq_start imm:$amt)]>;
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def ADJCALLSTACKUP : PseudoInstMips<(outs), (ins uimm16:$amt),
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"!ADJCALLSTACKUP $amt",
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[(callseq_end imm:$amt)]>;
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}
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def IMPLICIT_DEF_CPURegs : Pseudo<(outs CPURegs:$dst), (ins),
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"!IMPLICIT_DEF $dst",
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[(set CPURegs:$dst, (undef))]>;
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def IMPLICIT_DEF_CPURegs : PseudoInstMips<(outs CPURegs:$dst), (ins),
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"!IMPLICIT_DEF $dst",
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[(set CPURegs:$dst, (undef))]>;
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// When handling PIC code the assembler needs .cpload and .cprestore
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// directives. If the real instructions corresponding these directives
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// are used, we have the same behavior, but get also a bunch of warnings
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// from the assembler.
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def CPLOAD: PseudoInstMips<(outs), (ins CPURegs:$reg),
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".set noreorder\n\t.cpload $reg\n\t.set reorder", []>;
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def CPRESTORE: PseudoInstMips<(outs), (ins uimm16:$loc),
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".cprestore $loc", []>;
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// Used on PIC code only, it loads the address of label into register reg. The
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// address is calculated from the global pointer ($gp) and is expanded by the
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// assembler into two instructions "lw" and "addiu".
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def LA: PseudoInstMips<(outs CPURegs:$dst), (ins addrlabel:$label),
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"la $dst, $label", []>;
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//===----------------------------------------------------------------------===//
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// Instruction definition
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@ -507,6 +528,7 @@ def : Pat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
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def : Pat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
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def : Pat<(MipsAdd CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
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(ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
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def : Pat<(MipsLoadAddr tglobaladdr:$in), (LA tglobaladdr:$in)>;
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// Mips does not have not, so we increase the operation
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def : Pat<(not CPURegs:$in),
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