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R600: Add IsExport bit to TableGen instruction definitions

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Tested-by: Aaron Watry <awatry@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188516 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2013-08-16 01:11:51 +00:00
parent e560d526a1
commit e7ac2ed1c2
6 changed files with 16 additions and 10 deletions
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13
lib/Target/R600/R600ControlFlowFinalizer.cpp
View File

@ -373,15 +373,6 @@ public:
case AMDGPU::CF_ALU:
I = MI;
AluClauses.push_back(MakeALUClause(MBB, I));
case AMDGPU::EG_ExportBuf:
case AMDGPU::EG_ExportSwz:
case AMDGPU::R600_ExportBuf:
case AMDGPU::R600_ExportSwz:
case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
case AMDGPU::RAT_WRITE_CACHELESS_64_eg:
case AMDGPU::RAT_WRITE_CACHELESS_128_eg:
case AMDGPU::RAT_STORE_DWORD32:
case AMDGPU::RAT_STORE_DWORD64:
DEBUG(dbgs() << CfCount << ":"; MI->dump(););
CfCount++;
break;
@ -491,6 +482,10 @@ public:
EmitALUClause(I, AluClauses[i], CfCount);
}
default:
if (TII->isExport(MI->getOpcode())) {
DEBUG(dbgs() << CfCount << ":"; MI->dump(););
CfCount++;
}
break;
}
}

3
lib/Target/R600/R600Defines.h
View File

@ -44,7 +44,8 @@ namespace R600_InstFlag {
TEX_INST = (1 << 13),
ALU_INST = (1 << 14),
LDS_1A = (1 << 15),
LDS_1A1D = (1 << 16)
LDS_1A1D = (1 << 16),
IS_EXPORT = (1 << 17)
};
}

2
lib/Target/R600/R600InstrFormats.td
View File

@ -29,6 +29,7 @@ class InstR600 <dag outs, dag ins, string asm, list<dag> pattern,
bit VTXInst = 0;
bit TEXInst = 0;
bit ALUInst = 0;
bit IsExport = 0;
let Namespace = "AMDGPU";
let OutOperandList = outs;
@ -53,6 +54,7 @@ class InstR600 <dag outs, dag ins, string asm, list<dag> pattern,
let TSFlags{14} = ALUInst;
let TSFlags{15} = LDS_1A;
let TSFlags{16} = LDS_1A1D;
let TSFlags{17} = IsExport;
}
//===----------------------------------------------------------------------===//

4
lib/Target/R600/R600InstrInfo.cpp
View File

@ -160,6 +160,10 @@ bool R600InstrInfo::isTransOnly(const MachineInstr *MI) const {
return isTransOnly(MI->getOpcode());
}
bool R600InstrInfo::isExport(unsigned Opcode) const {
return (get(Opcode).TSFlags & R600_InstFlag::IS_EXPORT);
}
bool R600InstrInfo::usesVertexCache(unsigned Opcode) const {
return ST.hasVertexCache() && IS_VTX(get(Opcode));
}

1
lib/Target/R600/R600InstrInfo.h
View File

@ -68,6 +68,7 @@ namespace llvm {
bool isTransOnly(unsigned Opcode) const;
bool isTransOnly(const MachineInstr *MI) const;
bool isExport(unsigned Opcode) const;
bool usesVertexCache(unsigned Opcode) const;
bool usesVertexCache(const MachineInstr *MI) const;

3
lib/Target/R600/R600Instructions.td
View File

@ -278,6 +278,7 @@ class EG_CF_RAT <bits <8> cfinst, bits <6> ratinst, bits<4> ratid, bits<4> mask,
let Inst{31-0} = Word0;
let Inst{63-32} = Word1;
let IsExport = 1;
}
@ -551,6 +552,7 @@ class ExportSwzInst : InstR600ISA<(
let elem_size = 3;
let Inst{31-0} = Word0;
let Inst{63-32} = Word1;
let IsExport = 1;
}
} // End usesCustomInserter = 1
@ -564,6 +566,7 @@ class ExportBufInst : InstR600ISA<(
let elem_size = 0;
let Inst{31-0} = Word0;
let Inst{63-32} = Word1;
let IsExport = 1;
}
//===----------------------------------------------------------------------===//