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Add intrinsics and feature flag for read/write FS/GS base instructions. Also add AVX2 feature flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143319 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1651,3 +1651,25 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_bmi_pext_64 : GCCBuiltin<"__builtin_ia32_pext_di">,
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def int_x86_bmi_pext_64 : GCCBuiltin<"__builtin_ia32_pext_di">,
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Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
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Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
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}
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}
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//===----------------------------------------------------------------------===//
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// FS/GS Base
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_rdfsbase_32 : GCCBuiltin<"__builtin_ia32_rdfsbase32">,
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Intrinsic<[llvm_i32_ty], []>;
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def int_x86_rdgsbase_32 : GCCBuiltin<"__builtin_ia32_rdgsbase32">,
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Intrinsic<[llvm_i32_ty], []>;
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def int_x86_rdfsbase_64 : GCCBuiltin<"__builtin_ia32_rdfsbase64">,
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Intrinsic<[llvm_i64_ty], []>;
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def int_x86_rdgsbase_64 : GCCBuiltin<"__builtin_ia32_rdgsbase64">,
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Intrinsic<[llvm_i64_ty], []>;
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def int_x86_wrfsbase_32 : GCCBuiltin<"__builtin_ia32_wrfsbase32">,
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Intrinsic<[], [llvm_i32_ty]>;
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def int_x86_wrgsbase_32 : GCCBuiltin<"__builtin_ia32_wrgsbase32">,
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Intrinsic<[], [llvm_i32_ty]>;
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def int_x86_wrfsbase_64 : GCCBuiltin<"__builtin_ia32_wrfsbase64">,
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Intrinsic<[], [llvm_i64_ty]>;
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def int_x86_wrgsbase_64 : GCCBuiltin<"__builtin_ia32_wrgsbase64">,
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Intrinsic<[], [llvm_i64_ty]>;
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}
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@ -82,6 +82,9 @@ def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true",
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def FeatureAVX : SubtargetFeature<"avx", "HasAVX", "true",
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def FeatureAVX : SubtargetFeature<"avx", "HasAVX", "true",
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"Enable AVX instructions">;
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"Enable AVX instructions">;
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def FeatureAVX2 : SubtargetFeature<"avx2", "HasAVX2", "true",
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"Enable AVX2 instructions",
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[FeatureAVX]>;
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def FeatureCLMUL : SubtargetFeature<"clmul", "HasCLMUL", "true",
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def FeatureCLMUL : SubtargetFeature<"clmul", "HasCLMUL", "true",
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"Enable carry-less multiplication instructions">;
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"Enable carry-less multiplication instructions">;
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def FeatureFMA3 : SubtargetFeature<"fma3", "HasFMA3", "true",
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def FeatureFMA3 : SubtargetFeature<"fma3", "HasFMA3", "true",
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@ -99,6 +102,8 @@ def FeatureRDRAND : SubtargetFeature<"rdrand", "HasRDRAND", "true",
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"Support RDRAND instruction">;
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"Support RDRAND instruction">;
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def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true",
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def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true",
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"Support 16-bit floating point conversion instructions">;
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"Support 16-bit floating point conversion instructions">;
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def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
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"Support FS/GS Base instructions">;
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def FeatureLZCNT : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
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def FeatureLZCNT : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
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"Support LZCNT instruction">;
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"Support LZCNT instruction">;
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def FeatureBMI : SubtargetFeature<"bmi", "HasBMI", "true",
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def FeatureBMI : SubtargetFeature<"bmi", "HasBMI", "true",
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@ -157,13 +162,14 @@ def : Proc<"corei7-avx", [FeatureSSE42, FeatureCMPXCHG16B,
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// Ivy Bridge
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// Ivy Bridge
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def : Proc<"core-avx-i", [FeatureSSE42, FeatureCMPXCHG16B,
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def : Proc<"core-avx-i", [FeatureSSE42, FeatureCMPXCHG16B,
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FeatureAES, FeatureCLMUL,
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FeatureAES, FeatureCLMUL,
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FeatureRDRAND, FeatureF16C]>;
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FeatureRDRAND, FeatureF16C, FeatureFSGSBase]>;
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// Haswell
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// Haswell
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// FIXME: Disabling AVX/AVX2 for now since it's not ready.
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def : Proc<"core-avx2", [FeatureSSE42, FeatureCMPXCHG16B, FeatureAES,
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def : Proc<"core-avx2", [FeatureSSE42, FeatureCMPXCHG16B, FeatureAES,
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FeatureCLMUL, FeatureRDRAND, FeatureF16C,
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FeatureCLMUL, FeatureRDRAND, FeatureF16C,
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FeatureFMA3, FeatureMOVBE, FeatureLZCNT,
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FeatureFSGSBase, FeatureFMA3, FeatureMOVBE,
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FeatureBMI, FeatureBMI2]>;
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FeatureLZCNT, FeatureBMI, FeatureBMI2]>;
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def : Proc<"k6", [FeatureMMX]>;
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def : Proc<"k6", [FeatureMMX]>;
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def : Proc<"k6-2", [Feature3DNow]>;
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def : Proc<"k6-2", [Feature3DNow]>;
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@ -194,9 +200,8 @@ def : Proc<"barcelona", [FeatureSSE3, FeatureSSE4A,
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Feature3DNowA, FeatureCMPXCHG16B,
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Feature3DNowA, FeatureCMPXCHG16B,
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FeatureSlowBTMem]>;
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FeatureSlowBTMem]>;
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def : Proc<"istanbul", [Feature3DNowA, FeatureCMPXCHG16B,
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def : Proc<"istanbul", [Feature3DNowA, FeatureCMPXCHG16B,
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FeatureSSE4A, Feature3DNowA]>;
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FeatureSSE4A]>;
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def : Proc<"shanghai", [Feature3DNowA, FeatureCMPXCHG16B, FeatureSSE4A,
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def : Proc<"shanghai", [Feature3DNowA, FeatureCMPXCHG16B, FeatureSSE4A]>;
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Feature3DNowA]>;
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def : Proc<"winchip-c6", [FeatureMMX]>;
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def : Proc<"winchip-c6", [FeatureMMX]>;
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def : Proc<"winchip2", [Feature3DNow]>;
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def : Proc<"winchip2", [Feature3DNow]>;
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@ -472,6 +472,7 @@ def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
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def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
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def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
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def HasAVX : Predicate<"Subtarget->hasAVX()">;
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def HasAVX : Predicate<"Subtarget->hasAVX()">;
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def HasAVX2 : Predicate<"Subtarget->hasAVX2()">;
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def HasXMMInt : Predicate<"Subtarget->hasXMMInt()">;
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def HasXMMInt : Predicate<"Subtarget->hasXMMInt()">;
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def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">;
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def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">;
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@ -482,6 +483,7 @@ def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
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def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">;
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def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">;
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def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">;
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def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">;
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def HasF16C : Predicate<"Subtarget->hasF16C()">;
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def HasF16C : Predicate<"Subtarget->hasF16C()">;
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def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">;
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def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">;
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def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">;
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def HasBMI : Predicate<"Subtarget->hasBMI()">;
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def HasBMI : Predicate<"Subtarget->hasBMI()">;
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def HasBMI2 : Predicate<"Subtarget->hasBMI2()">;
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def HasBMI2 : Predicate<"Subtarget->hasBMI2()">;
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@ -446,23 +446,31 @@ let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// FS/GS Base Instructions
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// FS/GS Base Instructions
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let Predicates = [In64BitMode] in {
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let Predicates = [HasFSGSBase, In64BitMode] in {
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def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins),
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def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins),
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"rdfsbase{l}\t$dst", []>, TB, XS;
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"rdfsbase{l}\t$dst",
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[(set GR32:$dst, (int_x86_rdfsbase_32))]>, TB, XS;
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def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins),
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def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins),
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"rdfsbase{q}\t$dst", []>, TB, XS;
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"rdfsbase{q}\t$dst",
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[(set GR64:$dst, (int_x86_rdfsbase_64))]>, TB, XS;
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def RDGSBASE : I<0xAE, MRM1r, (outs GR32:$dst), (ins),
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def RDGSBASE : I<0xAE, MRM1r, (outs GR32:$dst), (ins),
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"rdgsbase{l}\t$dst", []>, TB, XS;
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"rdgsbase{l}\t$dst",
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[(set GR32:$dst, (int_x86_rdgsbase_32))]>, TB, XS;
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def RDGSBASE64 : RI<0xAE, MRM1r, (outs GR64:$dst), (ins),
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def RDGSBASE64 : RI<0xAE, MRM1r, (outs GR64:$dst), (ins),
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"rdgsbase{q}\t$dst", []>, TB, XS;
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"rdgsbase{q}\t$dst",
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def WRFSBASE : I<0xAE, MRM2r, (outs), (ins GR32:$dst),
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[(set GR64:$dst, (int_x86_rdgsbase_64))]>, TB, XS;
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"wrfsbase{l}\t$dst", []>, TB, XS;
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def WRFSBASE : I<0xAE, MRM2r, (outs), (ins GR32:$src),
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def WRFSBASE64 : RI<0xAE, MRM2r, (outs), (ins GR64:$dst),
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"wrfsbase{l}\t$src",
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"wrfsbase{q}\t$dst", []>, TB, XS;
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[(int_x86_wrfsbase_32 GR32:$src)]>, TB, XS;
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def WRGSBASE : I<0xAE, MRM3r, (outs), (ins GR32:$dst),
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def WRFSBASE64 : RI<0xAE, MRM2r, (outs), (ins GR64:$src),
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"wrgsbase{l}\t$dst", []>, TB, XS;
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"wrfsbase{q}\t$src",
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def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$dst),
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[(int_x86_wrfsbase_64 GR64:$src)]>, TB, XS;
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"wrgsbase{q}\t$dst", []>, TB, XS;
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def WRGSBASE : I<0xAE, MRM3r, (outs), (ins GR32:$src),
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"wrgsbase{l}\t$src",
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[(int_x86_wrgsbase_32 GR32:$src)]>, TB, XS;
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def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$src),
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"wrgsbase{q}\t$src",
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[(int_x86_wrgsbase_64 GR64:$src)]>, TB, XS;
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}
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}
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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@ -279,10 +279,19 @@ void X86Subtarget::AutoDetectSubtargetFeatures() {
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if (IsIntel && MaxLevel >= 7) {
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if (IsIntel && MaxLevel >= 7) {
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if (!X86_MC::GetCpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX)) {
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if (!X86_MC::GetCpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX)) {
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if (EBX & 0x1) {
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HasFSGSBase = true;
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ToggleFeature(X86::FeatureFSGSBase);
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}
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if ((EBX >> 3) & 0x1) {
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if ((EBX >> 3) & 0x1) {
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HasBMI = true;
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HasBMI = true;
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ToggleFeature(X86::FeatureBMI);
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ToggleFeature(X86::FeatureBMI);
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}
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}
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// FIXME: AVX2 codegen support is not ready.
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//if ((EBX >> 5) & 0x1) {
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// HasAVX2 = true;
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// ToggleFeature(X86::FeatureAVX2);
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//}
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if ((EBX >> 8) & 0x1) {
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if ((EBX >> 8) & 0x1) {
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HasBMI2 = true;
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HasBMI2 = true;
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ToggleFeature(X86::FeatureBMI2);
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ToggleFeature(X86::FeatureBMI2);
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@ -303,6 +312,7 @@ X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU,
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, HasPOPCNT(false)
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, HasPOPCNT(false)
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, HasSSE4A(false)
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, HasSSE4A(false)
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, HasAVX(false)
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, HasAVX(false)
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, HasAVX2(false)
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, HasAES(false)
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, HasAES(false)
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, HasCLMUL(false)
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, HasCLMUL(false)
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, HasFMA3(false)
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, HasFMA3(false)
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@ -310,6 +320,7 @@ X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU,
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, HasMOVBE(false)
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, HasMOVBE(false)
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, HasRDRAND(false)
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, HasRDRAND(false)
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, HasF16C(false)
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, HasF16C(false)
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, HasFSGSBase(false)
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, HasLZCNT(false)
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, HasLZCNT(false)
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, HasBMI(false)
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, HasBMI(false)
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, HasBMI2(false)
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, HasBMI2(false)
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@ -78,6 +78,9 @@ protected:
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/// HasAVX - Target has AVX instructions
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/// HasAVX - Target has AVX instructions
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bool HasAVX;
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bool HasAVX;
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/// HasAVX2 - Target has AVX2 instructions
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bool HasAVX2;
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/// HasAES - Target has AES instructions
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/// HasAES - Target has AES instructions
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bool HasAES;
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bool HasAES;
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@ -99,6 +102,9 @@ protected:
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/// HasF16C - Processor has 16-bit floating point conversion instructions.
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/// HasF16C - Processor has 16-bit floating point conversion instructions.
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bool HasF16C;
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bool HasF16C;
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/// HasFSGSBase - Processor has FS/GS base insturctions.
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bool HasFSGSBase;
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/// HasLZCNT - Processor has LZCNT instruction.
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/// HasLZCNT - Processor has LZCNT instruction.
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bool HasLZCNT;
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bool HasLZCNT;
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@ -181,6 +187,7 @@ public:
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bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
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bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
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bool hasPOPCNT() const { return HasPOPCNT; }
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bool hasPOPCNT() const { return HasPOPCNT; }
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bool hasAVX() const { return HasAVX; }
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bool hasAVX() const { return HasAVX; }
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bool hasAVX2() const { return HasAVX2; }
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bool hasXMM() const { return hasSSE1() || hasAVX(); }
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bool hasXMM() const { return hasSSE1() || hasAVX(); }
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bool hasXMMInt() const { return hasSSE2() || hasAVX(); }
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bool hasXMMInt() const { return hasSSE2() || hasAVX(); }
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bool hasAES() const { return HasAES; }
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bool hasAES() const { return HasAES; }
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@ -190,6 +197,7 @@ public:
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bool hasMOVBE() const { return HasMOVBE; }
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bool hasMOVBE() const { return HasMOVBE; }
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bool hasRDRAND() const { return HasRDRAND; }
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bool hasRDRAND() const { return HasRDRAND; }
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bool hasF16C() const { return HasF16C; }
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bool hasF16C() const { return HasF16C; }
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bool hasFSGSBase() const { return HasFSGSBase; }
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bool hasLZCNT() const { return HasLZCNT; }
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bool hasLZCNT() const { return HasLZCNT; }
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bool hasBMI() const { return HasBMI; }
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bool hasBMI() const { return HasBMI; }
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bool hasBMI2() const { return HasBMI2; }
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bool hasBMI2() const { return HasBMI2; }
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