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Now that register allocation properly considers reserved regs, simplify the

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ARM register class allocation order functions to take advantage of that.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112841 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2010-09-02 18:14:29 +00:00
parent 040bbcc876
commit e7c1416263
5 changed files with 26 additions and 162 deletions
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8
test/CodeGen/Thumb2/ldr-str-imm12.ll
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@@ -22,7 +22,7 @@
define %union.rec* @Manifest(%union.rec* %x, %union.rec* %env, %struct.STYLE* %style, %union.rec** %bthr, %union.rec** %fthr, %union.rec** %target, %union.rec** %crs, i32 %ok, i32 %need_expand, %union.rec** %enclose, i32 %fcr) nounwind {
entry:
; CHECK: ldr.w r9, [r7, #28]
; CHECK: ldr.w {{(r[0-9])|(lr)}}, [r7, #28]
%xgaps.i = alloca [32 x %union.rec*], align 4 ; <[32 x %union.rec*]*> [#uses=0]
%ycomp.i = alloca [32 x %union.rec*], align 4 ; <[32 x %union.rec*]*> [#uses=0]
br label %bb20
@@ -46,9 +46,9 @@ bb119: ; preds = %bb20, %bb20
bb420: ; preds = %bb20, %bb20
; CHECK: bb420
; CHECK: str r{{[0-7]}}, [sp]
; CHECK: str r{{[0-7]}}, [sp, #4]
; CHECK: str r{{[0-7]}}, [sp, #8]
; CHECK: str{{(.w)?}} r{{[0-9]+}}, [sp]
; CHECK: str{{(.w)?}} r{{[0-9]+}}, [sp, #4]
; CHECK: str{{(.w)?}} r{{[0-9]+}}, [sp, #8]
; CHECK: str{{(.w)?}} r{{[0-9]+}}, [sp, #24]
store %union.rec* null, %union.rec** @zz_hold, align 4
store %union.rec* null, %union.rec** @zz_res, align 4