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[Thumb2] RFE, SRS and "SUBS pc, lr" are undefined on v7M

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These instructions are related to the v7[AR] exception model, and are
not defined on v7M.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220204 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Oliver Stannard 2014-10-20 15:37:35 +00:00
parent 958df22c9f
commit e7c9c44387
2 changed files with 20 additions and 3 deletions
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8
lib/Target/ARM/ARMInstrThumb2.td
View File

@ -3757,7 +3757,8 @@ def t2DCPS3 : T2DCPS<0b11, "dcps3">;
class T2SRS<bits<2> Op, bit W, dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: T2I<oops, iops, itin, opc, asm, pattern> {
: T2I<oops, iops, itin, opc, asm, pattern>,
Requires<[IsThumb2,IsNotMClass]> {
bits<5> mode;
let Inst{31-25} = 0b1110100;
let Inst{24-23} = Op;
@ -3788,7 +3789,8 @@ def : t2InstAlias<"srsia${p} $mode!", (t2SRSIA_UPD imm0_31:$mode, pred:$p)>;
// Return From Exception is a system instruction.
class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: T2I<oops, iops, itin, opc, asm, pattern> {
: T2I<oops, iops, itin, opc, asm, pattern>,
Requires<[IsThumb2,IsNotMClass]> {
let Inst{31-20} = op31_20{11-0};
bits<4> Rn;
@ -3815,7 +3817,7 @@ let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in
def t2SUBS_PC_LR : T2I <(outs), (ins imm0_255:$imm), NoItinerary,
"subs", "\tpc, lr, $imm",
[(ARMintretflag imm0_255:$imm)]>,
Requires<[IsThumb2]> {
Requires<[IsThumb2,IsNotMClass]> {
let Inst{31-8} = 0b111100111101111010001111;
bits<8> imm;

15
test/MC/ARM/thumb2-exception-return-mclass.s Normal file
View File

@ -0,0 +1,15 @@
# RUN: not llvm-mc -triple thumbv7m -assemble < %s 2>&1 | FileCheck %s
.text
# CHECK: instruction requires: !armv*m
# CHECK-NEXT: srsdb sp, #7
srsdb sp, #7
# CHECK: instruction requires: !armv*m
# CHECK-NEXT: rfeia r6
rfeia r6
# CHECK: instruction requires: !armv*m
# CHECK-NEXT: subs pc, lr, #42
subs pc, lr, #42