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Add a ARM specific pre-allocation pass that re-schedule loads / stores from

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consecutive addresses togther. This makes it easier for the post-allocation pass
to form ldm / stm.

This is step 1. We are still missing a lot of ldm / stm opportunities because
of register allocation are not done in the desired order. More enhancements
coming.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73291 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2009-06-13 09:12:55 +00:00
parent daf9e02893
commit e7d6df7353
6 changed files with 347 additions and 28 deletions
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lib/CodeGen/LLVMTargetMachine.cpp
+1 -1
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@@ -240,7 +240,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
if (OptLevel != CodeGenOpt::None) {
PM.add(createMachineLICMPass());
PM.add(createMachineSinkingPass());
printAndVerify(PM, /* allowDoubleDefs= */ true);
printAndVerify(PM, /* allowDoubleDefs= */ false);
}
// Run pre-ra passes.