Skeleton of post-RA scheduler; doesn't do anything yet.

Change name of -sched option and DEBUG_TYPE to
pre-RA-sched; adjust testcases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39816 91177308-0d34-0410-b5e6-96231b3b80d8

include/llvm/CodeGen/Passes.h

@@ -89,6 +89,9 @@ namespace llvm {
   ///
   FunctionPass *createPrologEpilogCodeInserter();
 
+  /// createPostRAScheduler - under development.
+  FunctionPass *createPostRAScheduler();
+
   /// BranchFolding Pass - This pass performs machine code CFG based
   /// optimizations to delete branches to branches, eliminate branches to
   /// successor blocks (creating fall throughs), and eliminating branches over

lib/CodeGen/LLVMTargetMachine.cpp

@@ -78,6 +78,9 @@ LLVMTargetMachine::addPassesToEmitFile(FunctionPassManager &PM,
   // Insert prolog/epilog code.  Eliminate abstract frame index references...
   PM.add(createPrologEpilogCodeInserter());
   
+  // Second pass scheduler.
+  PM.add(createPostRAScheduler());
+
   // Branch folding must be run after regalloc and prolog/epilog insertion.
   if (!Fast)
     PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
@@ -181,6 +184,9 @@ bool LLVMTargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
   if (PrintMachineCode)  // Print the register-allocated code
     PM.add(createMachineFunctionPrinterPass(cerr));
   
+  // Second pass scheduler.
+  PM.add(createPostRAScheduler());
+
   // Branch folding must be run after regalloc and prolog/epilog insertion.
   if (!Fast)
     PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));

lib/CodeGen/PostRASchedulerList.cpp

@@ -0,0 +1,81 @@
+//===----- SchedulePostRAList.cpp - list scheduler ----===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file was developed by Dale Johannesen and is distributed under the
+// University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This implements a top-down list scheduler, using standard algorithms.
+// The basic approach uses a priority queue of available nodes to schedule.
+// One at a time, nodes are taken from the priority queue (thus in priority
+// order), checked for legality to schedule, and emitted if legal.
+//
+// Nodes may not be legal to schedule either due to structural hazards (e.g.
+// pipeline or resource constraints) or because an input to the instruction has
+// not completed execution.
+//
+//===----------------------------------------------------------------------===//
+
+#define DEBUG_TYPE "post-RA-sched"
+#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/Support/Debug.h"
+//#include "llvm/ADT/Statistic.h"
+//#include <climits>
+//#include <queue>
+#include "llvm/Support/CommandLine.h"
+using namespace llvm;
+
+namespace {
+  bool NoPostRAScheduling;
+
+  // When this works it will be on by default.
+  cl::opt<bool, true>
+  DisablePostRAScheduler("disable-post-RA-scheduler",
+               cl::desc("Disable scheduling after register allocation"),
+               cl::location(NoPostRAScheduling),
+               cl::init(true));
+
+  class VISIBILITY_HIDDEN SchedulePostRATDList : public MachineFunctionPass {
+  public:
+    static char ID;
+    SchedulePostRATDList() : MachineFunctionPass((intptr_t)&ID) {}
+  private:
+    MachineFunction *MF;
+    const TargetMachine *TM;
+  public:
+    const char *getPassName() const {
+      return "Post RA top-down list latency scheduler (STUB)";
+    }
+
+    bool runOnMachineFunction(MachineFunction &Fn);
+  };
+  char SchedulePostRATDList::ID = 0;
+}
+
+bool SchedulePostRATDList::runOnMachineFunction(MachineFunction &Fn) {
+  if (NoPostRAScheduling)
+    return true;
+
+  DOUT << "SchedulePostRATDList\n";
+  MF = &Fn;
+  TM = &MF->getTarget();
+
+  // Loop over all of the basic blocks
+  for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
+       MBB != MBBe; ++MBB)
+    ;
+
+  return true;
+}
+  
+
+//===----------------------------------------------------------------------===//
+//                         Public Constructor Functions
+//===----------------------------------------------------------------------===//
+
+FunctionPass *llvm::createPostRAScheduler() {
+  return new SchedulePostRATDList();
+}

lib/CodeGen/SelectionDAG/ScheduleDAG.cpp

@@ -13,7 +13,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-#define DEBUG_TYPE "sched"
+#define DEBUG_TYPE "pre-RA-sched"
 #include "llvm/Type.h"
 #include "llvm/CodeGen/ScheduleDAG.h"
 #include "llvm/CodeGen/MachineConstantPool.h"

lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp

@@ -18,7 +18,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-#define DEBUG_TYPE "sched"
+#define DEBUG_TYPE "pre-RA-sched"
 #include "llvm/CodeGen/ScheduleDAG.h"
 #include "llvm/CodeGen/SchedulerRegistry.h"
 #include "llvm/CodeGen/SelectionDAGISel.h"

lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

@@ -15,7 +15,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-#define DEBUG_TYPE "sched"
+#define DEBUG_TYPE "pre-RA-sched"
 #include "llvm/CodeGen/ScheduleDAG.h"
 #include "llvm/CodeGen/SchedulerRegistry.h"
 #include "llvm/CodeGen/SSARegMap.h"

lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp

@@ -13,7 +13,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-#define DEBUG_TYPE "sched"
+#define DEBUG_TYPE "pre-RA-sched"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/ScheduleDAG.h"
 #include "llvm/CodeGen/SchedulerRegistry.h"

lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

@@ -73,9 +73,9 @@ MachinePassRegistry RegisterScheduler::Registry;
 namespace {
   cl::opt<RegisterScheduler::FunctionPassCtor, false,
           RegisterPassParser<RegisterScheduler> >
-  ISHeuristic("sched",
+  ISHeuristic("pre-RA-sched",
               cl::init(&createDefaultScheduler),
-              cl::desc("Instruction schedulers available:"));
+              cl::desc("Instruction schedulers available (before register allocation):"));
 
   static RegisterScheduler
   defaultListDAGScheduler("default", "  Best scheduler for the target",

lib/Target/PowerPC/PPCHazardRecognizers.cpp

@@ -11,7 +11,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-#define DEBUG_TYPE "sched"
+#define DEBUG_TYPE "pre-RA-sched"
 #include "PPCHazardRecognizers.h"
 #include "PPC.h"
 #include "PPCInstrInfo.h"

test/CodeGen/Generic/2006-07-03-schedulers.ll

@@ -1,10 +1,10 @@
-; RUN: llvm-upgrade %s | llvm-as | llc -sched=none
+; RUN: llvm-upgrade %s | llvm-as | llc -pre-RA-sched=none
-; RUN: llvm-upgrade %s | llvm-as | llc -sched=default
+; RUN: llvm-upgrade %s | llvm-as | llc -pre-RA-sched=default
-; RUN: llvm-upgrade %s | llvm-as | llc -sched=simple
+; RUN: llvm-upgrade %s | llvm-as | llc -pre-RA-sched=simple
-; RUN: llvm-upgrade %s | llvm-as | llc -sched=simple-noitin
+; RUN: llvm-upgrade %s | llvm-as | llc -pre-RA-sched=simple-noitin
-; RUN: llvm-upgrade %s | llvm-as | llc -sched=list-td
+; RUN: llvm-upgrade %s | llvm-as | llc -pre-RA-sched=list-td
-; RUN: llvm-upgrade %s | llvm-as | llc -sched=list-tdrr
+; RUN: llvm-upgrade %s | llvm-as | llc -pre-RA-sched=list-tdrr
-; RUN: llvm-upgrade %s | llvm-as | llc -sched=list-burr
+; RUN: llvm-upgrade %s | llvm-as | llc -pre-RA-sched=list-burr
 ; PR859
 
 implementation

test/CodeGen/X86/2007-01-13-StackPtrIndex.ll

@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86-64 -sched=none | grep leaq
+; RUN: llvm-as < %s | llc -march=x86-64 -pre-RA-sched=none | grep leaq
-; RUN: llvm-as < %s | llc -march=x86-64 -sched=none | not grep {,%rsp)}
+; RUN: llvm-as < %s | llc -march=x86-64 -pre-RA-sched=none | not grep {,%rsp)}
 ; PR1103
 
 target datalayout = "e-p:64:64"