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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-23 02:29:18 +00:00
Remove intrinsic specific instructions for (V)CVTPS2DQ and replace with patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159109 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -410,7 +410,6 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
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{ X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
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{ X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
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{ X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
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{ X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm, 0 },
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{ X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 },
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{ X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 },
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{ X86::CVTSS2SI64rr, X86::CVTSS2SI64rm, 0 },
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@ -491,7 +490,6 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
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// AVX 128-bit versions of foldable instructions
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{ X86::Int_VCOMISDrr, X86::Int_VCOMISDrm, 0 },
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{ X86::Int_VCOMISSrr, X86::Int_VCOMISSrm, 0 },
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{ X86::Int_VCVTPS2PDrr, X86::Int_VCVTPS2PDrm, 0 },
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{ X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, 0 },
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{ X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, 0 },
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{ X86::VCVTTSD2SI64rr, X86::VCVTTSD2SI64rm, 0 },
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@ -2020,28 +2020,15 @@ def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
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"cvtps2pd\t{$src, $dst|$dst, $src}", [],
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IIC_SSE_CVT_PD_RM>, TB;
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def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"vcvtps2pd\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
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IIC_SSE_CVT_PD_RR>,
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TB, VEX, Requires<[HasAVX]>;
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def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
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"vcvtps2pd\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtps2pd
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(load addr:$src)))],
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IIC_SSE_CVT_PD_RM>,
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TB, VEX, Requires<[HasAVX]>;
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def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvtps2pd\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
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IIC_SSE_CVT_PD_RR>,
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TB, Requires<[HasSSE2]>;
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def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
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"cvtps2pd\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtps2pd
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(load addr:$src)))],
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IIC_SSE_CVT_PD_RM>,
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TB, Requires<[HasSSE2]>;
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let Predicates = [HasAVX] in {
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def : Pat<(int_x86_sse2_cvtps2pd VR128:$src),
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(VCVTPS2PDrr VR128:$src)>;
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}
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let Predicates = [HasSSE2] in {
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def : Pat<(int_x86_sse2_cvtps2pd VR128:$src),
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(CVTPS2PDrr VR128:$src)>;
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}
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// Convert Packed DW Integers to Packed Double FP
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let Predicates = [HasAVX] in {
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