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Rename the load and store opcodes. The non-fp ones only have one
variant worth worrying about; the fp ones have two. Add fp stores. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14361 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -59,23 +59,36 @@ let rd = 0 in
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def CMPri: F3_2<2, 0b010100, "cmp">;
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// Section B.1 - Load Integer Instructions, p. 90
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def LDSBmr: F3_2<3, 0b001001, "ldsb">;
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def LDSHmr: F3_2<3, 0b001010, "ldsh">;
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def LDUBmr: F3_2<3, 0b000001, "ldub">;
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def LDUHmr: F3_2<3, 0b000010, "lduh">;
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def LDmr : F3_2<3, 0b000000, "ld">;
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def LDDmr : F3_2<3, 0b000011, "ldd">;
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def LDSB: F3_2<3, 0b001001, "ldsb">;
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def LDSH: F3_2<3, 0b001010, "ldsh">;
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def LDUB: F3_2<3, 0b000001, "ldub">;
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def LDUH: F3_2<3, 0b000010, "lduh">;
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def LD : F3_2<3, 0b000000, "ld">;
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def LDD : F3_2<3, 0b000011, "ldd">;
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// Section B.2 - Load Floating-point Instructions, p. 92
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def LDFmr : F3_2<3, 0b100000, "ld">;
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def LDDFmr : F3_2<3, 0b100011, "ldd">;
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def LDFSRmr: F3_2<3, 0b100001, "ld">;
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def LDFrr : F3_1<3, 0b100000, "ld">;
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def LDFri : F3_2<3, 0b100000, "ld">;
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def LDDFrr : F3_1<3, 0b100011, "ldd">;
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def LDDFri : F3_2<3, 0b100011, "ldd">;
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def LDFSRrr: F3_1<3, 0b100001, "ld">;
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def LDFSRri: F3_2<3, 0b100001, "ld">;
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// Section B.4 - Store Integer Instructions, p. 95
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def STBrm : F3_2<3, 0b000101, "stb">;
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def STHrm : F3_2<3, 0b000110, "sth">;
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def STrm : F3_2<3, 0b000100, "st">;
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def STDrm : F3_2<3, 0b000111, "std">;
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def STB : F3_2<3, 0b000101, "stb">;
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def STH : F3_2<3, 0b000110, "sth">;
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def ST : F3_2<3, 0b000100, "st">;
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def STD : F3_2<3, 0b000111, "std">;
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// Section B.5 - Store Floating-point Instructions, p. 97
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def STFrr : F3_1<3, 0b100100, "st">;
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def STFri : F3_2<3, 0b100100, "st">;
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def STDFrr : F3_1<3, 0b100111, "std">;
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def STDFri : F3_2<3, 0b100111, "std">;
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def STFSRrr : F3_1<3, 0b100101, "st">;
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def STFSRri : F3_2<3, 0b100101, "st">;
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def STDFQrr : F3_1<3, 0b100110, "std">;
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def STDFQri : F3_2<3, 0b100110, "std">;
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// Section B.9 - SETHI Instruction, p. 104
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def SETHIi: F2_1<0b100, "sethi">;
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@ -59,23 +59,36 @@ let rd = 0 in
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def CMPri: F3_2<2, 0b010100, "cmp">;
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// Section B.1 - Load Integer Instructions, p. 90
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def LDSBmr: F3_2<3, 0b001001, "ldsb">;
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def LDSHmr: F3_2<3, 0b001010, "ldsh">;
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def LDUBmr: F3_2<3, 0b000001, "ldub">;
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def LDUHmr: F3_2<3, 0b000010, "lduh">;
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def LDmr : F3_2<3, 0b000000, "ld">;
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def LDDmr : F3_2<3, 0b000011, "ldd">;
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def LDSB: F3_2<3, 0b001001, "ldsb">;
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def LDSH: F3_2<3, 0b001010, "ldsh">;
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def LDUB: F3_2<3, 0b000001, "ldub">;
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def LDUH: F3_2<3, 0b000010, "lduh">;
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def LD : F3_2<3, 0b000000, "ld">;
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def LDD : F3_2<3, 0b000011, "ldd">;
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// Section B.2 - Load Floating-point Instructions, p. 92
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def LDFmr : F3_2<3, 0b100000, "ld">;
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def LDDFmr : F3_2<3, 0b100011, "ldd">;
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def LDFSRmr: F3_2<3, 0b100001, "ld">;
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def LDFrr : F3_1<3, 0b100000, "ld">;
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def LDFri : F3_2<3, 0b100000, "ld">;
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def LDDFrr : F3_1<3, 0b100011, "ldd">;
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def LDDFri : F3_2<3, 0b100011, "ldd">;
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def LDFSRrr: F3_1<3, 0b100001, "ld">;
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def LDFSRri: F3_2<3, 0b100001, "ld">;
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// Section B.4 - Store Integer Instructions, p. 95
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def STBrm : F3_2<3, 0b000101, "stb">;
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def STHrm : F3_2<3, 0b000110, "sth">;
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def STrm : F3_2<3, 0b000100, "st">;
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def STDrm : F3_2<3, 0b000111, "std">;
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def STB : F3_2<3, 0b000101, "stb">;
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def STH : F3_2<3, 0b000110, "sth">;
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def ST : F3_2<3, 0b000100, "st">;
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def STD : F3_2<3, 0b000111, "std">;
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// Section B.5 - Store Floating-point Instructions, p. 97
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def STFrr : F3_1<3, 0b100100, "st">;
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def STFri : F3_2<3, 0b100100, "st">;
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def STDFrr : F3_1<3, 0b100111, "std">;
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def STDFri : F3_2<3, 0b100111, "std">;
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def STFSRrr : F3_1<3, 0b100101, "st">;
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def STFSRri : F3_2<3, 0b100101, "st">;
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def STDFQrr : F3_1<3, 0b100110, "std">;
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def STDFQri : F3_2<3, 0b100110, "std">;
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// Section B.9 - SETHI Instruction, p. 104
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def SETHIi: F2_1<0b100, "sethi">;
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