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use predicates in DBG_VALUE printing code to simplify it.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100312 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2010-04-04 05:21:31 +00:00
parent 88db786712
commit e812d4c604
1 changed files with 9 additions and 10 deletions
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19
lib/Target/X86/AsmPrinter/X86MCInstLower.cpp
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@ -344,16 +344,17 @@ void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
O << " <- "; O << " <- ";
if (NOps==3) { if (NOps==3) {
// Register or immediate value. Register 0 means undef. // Register or immediate value. Register 0 means undef.
assert(MI->getOperand(0).getType()==MachineOperand::MO_Register || assert(MI->getOperand(0).isReg() ||
MI->getOperand(0).getType()==MachineOperand::MO_Immediate || MI->getOperand(0).isImm() ||
MI->getOperand(0).getType()==MachineOperand::MO_FPImmediate); MI->getOperand(0).isFPImm());
if (MI->getOperand(0).getType()==MachineOperand::MO_Register && if (MI->getOperand(0).isReg() && MI->getOperand(0).getReg() == 0) {
MI->getOperand(0).getReg()==0) {
// Suppress offset in this case, it is not meaningful. // Suppress offset in this case, it is not meaningful.
O << "undef"; O << "undef";
OutStreamer.AddBlankLine(); OutStreamer.AddBlankLine();
return; return;
} else if (MI->getOperand(0).getType()==MachineOperand::MO_FPImmediate) { }
if (MI->getOperand(0).isFPImm()) {
// This is more naturally done in printOperand, but since the only use // This is more naturally done in printOperand, but since the only use
// of such an operand is in this comment and that is temporary (and it's // of such an operand is in this comment and that is temporary (and it's
// ugly), we prefer to keep this localized. // ugly), we prefer to keep this localized.
@ -373,16 +374,14 @@ void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
} else } else
printOperand(MI, 0, O); printOperand(MI, 0, O);
} else { } else {
if (MI->getOperand(0).getType()==MachineOperand::MO_Register && if (MI->getOperand(0).isReg() && MI->getOperand(0).getReg() == 0) {
MI->getOperand(0).getReg()==0) {
// Suppress offset in this case, it is not meaningful. // Suppress offset in this case, it is not meaningful.
O << "undef"; O << "undef";
OutStreamer.AddBlankLine(); OutStreamer.AddBlankLine();
return; return;
} }
// Frame address. Currently handles register +- offset only. // Frame address. Currently handles register +- offset only.
assert(MI->getOperand(0).getType()==MachineOperand::MO_Register); assert(MI->getOperand(0).isReg() && MI->getOperand(3).isImm());
assert(MI->getOperand(3).getType()==MachineOperand::MO_Immediate);
O << '['; printOperand(MI, 0, O); O << '+'; printOperand(MI, 3, O); O << '['; printOperand(MI, 0, O); O << '+'; printOperand(MI, 3, O);
O << ']'; O << ']';
} }