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- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and

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sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2011-06-28 19:10:37 +00:00
parent 9bbe4d6c00
commit e837dead3c
77 changed files with 903 additions and 875 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/Target/SystemZ/SystemZInstrInfo.cpp
+6 -6
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@@ -199,13 +199,13 @@ ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
}
bool SystemZInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
const TargetInstrDesc &TID = MI->getDesc();
if (!TID.isTerminator()) return false;
const MCInstrDesc &MCID = MI->getDesc();
if (!MCID.isTerminator()) return false;
// Conditional branch is a special case.
if (TID.isBranch() && !TID.isBarrier())
if (MCID.isBranch() && !MCID.isBarrier())
return true;
if (!TID.isPredicable())
if (!MCID.isPredicable())
return true;
return !isPredicated(MI);
}
@@ -343,7 +343,7 @@ SystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
return Count;
}
const TargetInstrDesc&
const MCInstrDesc&
SystemZInstrInfo::getBrCond(SystemZCC::CondCodes CC) const {
switch (CC) {
default:
@@ -408,7 +408,7 @@ SystemZInstrInfo::getOppositeCondition(SystemZCC::CondCodes CC) const {
}
}
const TargetInstrDesc&
const MCInstrDesc&
SystemZInstrInfo::getLongDispOpc(unsigned Opc) const {
switch (Opc) {
default: