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This commit introduces two fake instructions MORESTACK_RET and

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MORESTACK_RET_RESTORE_R10; which are lowered to a RET and a RET
followed by a MOV respectively.  Having a fake instruction prevents
the verifier from seeing a MachineBasicBlock end with a
non-terminator (MOV).  It also prevents the rather eccentric case of a
MachineBasicBlock ending with RET but having successors nevertheless.

Patch by Sanjoy Das.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143062 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola 2011-10-26 21:12:27 +00:00
parent 75757f9fd1
commit e840e88239
4 changed files with 41 additions and 23 deletions
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28
lib/Target/X86/X86FrameLowering.cpp
View File

@ -1336,26 +1336,16 @@ X86FrameLowering::adjustForSegmentedStacks(MachineFunction &MF) const {
// The MOV R10, RAX needs to be in a different block, since the RET we emit in
// allocMBB needs to be last (terminating) instruction.
MachineBasicBlock *restoreR10MBB = NULL;
if (IsNested)
restoreR10MBB = MF.CreateMachineBasicBlock();
for (MachineBasicBlock::livein_iterator i = prologueMBB.livein_begin(),
e = prologueMBB.livein_end(); i != e; i++) {
allocMBB->addLiveIn(*i);
checkMBB->addLiveIn(*i);
if (IsNested)
restoreR10MBB->addLiveIn(*i);
}
if (IsNested) {
allocMBB->addLiveIn(X86::R10);
restoreR10MBB->addLiveIn(X86::RAX);
}
if (IsNested)
MF.push_front(restoreR10MBB);
allocMBB->addLiveIn(X86::R10);
MF.push_front(allocMBB);
MF.push_front(checkMBB);
@ -1425,18 +1415,12 @@ X86FrameLowering::adjustForSegmentedStacks(MachineFunction &MF) const {
if (!Is64Bit)
BuildMI(allocMBB, DL, TII.get(X86::ADD32ri), X86::ESP).addReg(X86::ESP)
.addImm(8);
BuildMI(allocMBB, DL, TII.get(X86::RET));
if (IsNested)
BuildMI(restoreR10MBB, DL, TII.get(X86::MOV64rr), X86::R10)
.addReg(X86::RAX);
BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET_RESTORE_R10));
else
BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET));
if (IsNested) {
allocMBB->addSuccessor(restoreR10MBB);
restoreR10MBB->addSuccessor(&prologueMBB);
} else {
allocMBB->addSuccessor(&prologueMBB);
}
allocMBB->addSuccessor(&prologueMBB);
checkMBB->addSuccessor(allocMBB);
checkMBB->addSuccessor(&prologueMBB);

18
lib/Target/X86/X86InstrCompiler.td
View File

@ -149,6 +149,24 @@ def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
}
//===----------------------------------------------------------------------===//
// Pseudo instructions used by segmented stacks.
//
// This is lowered into a RET instruction by MCInstLower. We need
// this so that we don't have to have a MachineBasicBlock which ends
// with a RET and also has successors.
let isPseudo = 1 in {
def MORESTACK_RET: I<0, Pseudo, (outs), (ins),
"", []>;
// This instruction is lowered to a RET followed by a MOV. The two
// instructions are not generated on a higher level since then the
// verifier sees a MachineBasicBlock ending with a non-terminator.
def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins),
"", []>;
}
//===----------------------------------------------------------------------===//
// Alias Instructions
//===----------------------------------------------------------------------===//

16
lib/Target/X86/X86MCInstLower.cpp
View File

@ -527,6 +527,22 @@ ReSimplify:
case X86::XOR16ri: SimplifyShortImmForm(OutMI, X86::XOR16i16); break;
case X86::XOR32ri: SimplifyShortImmForm(OutMI, X86::XOR32i32); break;
case X86::XOR64ri32: SimplifyShortImmForm(OutMI, X86::XOR64i32); break;
case X86::MORESTACK_RET:
OutMI.setOpcode(X86::RET);
break;
case X86::MORESTACK_RET_RESTORE_R10: {
MCInst retInst;
OutMI.setOpcode(X86::MOV64rr);
OutMI.addOperand(MCOperand::CreateReg(X86::R10));
OutMI.addOperand(MCOperand::CreateReg(X86::RAX));
retInst.setOpcode(X86::RET);
AsmPrinter.OutStreamer.EmitInstruction(retInst);
break;
}
}
}

2
test/CodeGen/X86/segmented-stacks.ll
View File

@ -82,6 +82,6 @@ define i32 @test_nested(i32 * nest %closure, i32 %other) {
; X64-NEXT: movabsq $0, %r11
; X64-NEXT: callq __morestack
; X64-NEXT: ret
; X64: movq %rax, %r10
; X64-NEXT: movq %rax, %r10
}