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Add UDIV, SDIV, and a few variants of WR.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12733 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Brian Gaeke 2004-04-07 04:01:00 +00:00
parent 2d4fa8faac
commit e88c9dc860
2 changed files with 16 additions and 0 deletions
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8
lib/Target/Sparc/SparcInstrInfo.td
View File

@ -94,6 +94,10 @@ def SUBrr : F3_1<2, 0b000100, "sub">;
def UMULrr : F3_1<2, 0b001010, "umul">;
def SMULrr : F3_1<2, 0b001011, "smul">;
// Section B.19 - Divide Instructions, p. 115
def UDIVrr: F3_1<2, 0b001110, "udiv">;
def SDIVrr: F3_1<2, 0b001111, "sdiv">;
// Section B.20 - SAVE and RESTORE, p. 117
def SAVErr : F3_1<2, 0b111100, "save">; // save r, r, r
def SAVEri : F3_2<2, 0b111100, "save">; // save r, i, r
@ -114,3 +118,7 @@ def CALL : InstV8 {
def JMPLrr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd
def JMPLri : F3_2<2, 0b111000, "jmpl">; // jmpl [rs1+imm], rd
// Section B.29 - Write State Register Instructions, p. 133
let rd = 0 in
def WRYrr : F3_1<2, 0b110000, "wr">; // Special case of WRASR
def WRASRrr : F3_1<2, 0b110000, "wr">; // Special reg = reg ^ reg

8
lib/Target/SparcV8/SparcV8InstrInfo.td
View File

@ -94,6 +94,10 @@ def SUBrr : F3_1<2, 0b000100, "sub">;
def UMULrr : F3_1<2, 0b001010, "umul">;
def SMULrr : F3_1<2, 0b001011, "smul">;
// Section B.19 - Divide Instructions, p. 115
def UDIVrr: F3_1<2, 0b001110, "udiv">;
def SDIVrr: F3_1<2, 0b001111, "sdiv">;
// Section B.20 - SAVE and RESTORE, p. 117
def SAVErr : F3_1<2, 0b111100, "save">; // save r, r, r
def SAVEri : F3_2<2, 0b111100, "save">; // save r, i, r
@ -114,3 +118,7 @@ def CALL : InstV8 {
def JMPLrr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd
def JMPLri : F3_2<2, 0b111000, "jmpl">; // jmpl [rs1+imm], rd
// Section B.29 - Write State Register Instructions, p. 133
let rd = 0 in
def WRYrr : F3_1<2, 0b110000, "wr">; // Special case of WRASR
def WRASRrr : F3_1<2, 0b110000, "wr">; // Special reg = reg ^ reg