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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-21 18:29:46 +00:00
Revert r160920 and r160919 due to dragonegg and clang selfhost failure
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160927 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -14,7 +14,6 @@
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#ifndef LLVM_TARGET_TARGETINSTRINFO_H
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#define LLVM_TARGET_TARGETINSTRINFO_H
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/CodeGen/DFAPacketizer.h"
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#include "llvm/CodeGen/MachineFunction.h"
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@ -694,16 +693,6 @@ public:
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return false;
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}
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/// optimizeLoadInstr - Try to remove the load by folding it to a register
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/// operand at the use. We fold the load instructions if and only if the
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/// def and use are in the same BB.
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virtual MachineInstr* optimizeLoadInstr(MachineInstr *MI,
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const MachineRegisterInfo *MRI,
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SmallSet<unsigned, 4> &FoldAsLoadDefRegs,
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MachineInstr *&DefMI) const {
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return 0;
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}
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/// FoldImmediate - 'Reg' is known to be defined by a move immediate
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/// instruction, try to fold the immediate into the use instruction.
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virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
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@ -78,7 +78,6 @@ STATISTIC(NumReuse, "Number of extension results reused");
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STATISTIC(NumBitcasts, "Number of bitcasts eliminated");
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STATISTIC(NumCmps, "Number of compares eliminated");
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STATISTIC(NumImmFold, "Number of move immediate folded");
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STATISTIC(NumLoadFold, "Number of loads folded");
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namespace {
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class PeepholeOptimizer : public MachineFunctionPass {
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@ -442,7 +441,6 @@ bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) {
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SmallPtrSet<MachineInstr*, 8> LocalMIs;
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SmallSet<unsigned, 4> ImmDefRegs;
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DenseMap<unsigned, MachineInstr*> ImmDefMIs;
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SmallSet<unsigned, 4> FoldAsLoadDefRegs;
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for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
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MachineBasicBlock *MBB = &*I;
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@ -450,7 +448,6 @@ bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) {
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LocalMIs.clear();
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ImmDefRegs.clear();
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ImmDefMIs.clear();
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FoldAsLoadDefRegs.clear();
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bool First = true;
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MachineBasicBlock::iterator PMII;
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@ -492,25 +489,6 @@ bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) {
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Changed |= foldImmediate(MI, MBB, ImmDefRegs, ImmDefMIs);
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}
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MachineInstr *DefMI = 0;
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MachineInstr *FoldMI = TII->optimizeLoadInstr(MI, MRI, FoldAsLoadDefRegs,
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DefMI);
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if (FoldMI) {
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// Update LocalMIs since we replaced MI with FoldMI and deleted DefMI.
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LocalMIs.erase(MI);
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LocalMIs.erase(DefMI);
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LocalMIs.insert(FoldMI);
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MI->eraseFromParent();
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DefMI->eraseFromParent();
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++NumLoadFold;
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// MI is replaced with FoldMI.
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Changed = true;
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PMII = FoldMI;
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MII = llvm::next(PMII);
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continue;
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}
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First = false;
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PMII = MII;
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++MII;
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@ -3323,75 +3323,6 @@ optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
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return true;
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}
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/// optimizeLoadInstr - Try to remove the load by folding it to a register
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/// operand at the use. We fold the load instructions if and only if the
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/// def and use are in the same BB.
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MachineInstr* X86InstrInfo::
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optimizeLoadInstr(MachineInstr *MI, const MachineRegisterInfo *MRI,
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SmallSet<unsigned, 4> &FoldAsLoadDefRegs,
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MachineInstr *&DefMI) const {
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if (MI->mayStore() || MI->isCall())
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// To be conservative, we don't fold the loads if there is a store in
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// between.
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FoldAsLoadDefRegs.clear();
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// We only fold loads to a virtual register.
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if (MI->canFoldAsLoad()) {
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const MCInstrDesc &MCID = MI->getDesc();
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if (MCID.getNumDefs() == 1) {
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unsigned Reg = MI->getOperand(0).getReg();
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// To reduce compilation time, we check MRI->hasOneUse when inserting
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// loads. It should be checked when processing uses of the load, since
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// uses can be removed during peephole.
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if (TargetRegisterInfo::isVirtualRegister(Reg) && MRI->hasOneUse(Reg)) {
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FoldAsLoadDefRegs.insert(Reg);
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return 0;
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}
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}
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}
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// Collect information about virtual register operands of MI.
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DenseMap<unsigned, unsigned> SrcVirtualRegToOp;
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SmallSet<unsigned, 4> DstVirtualRegs;
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for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg())
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continue;
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unsigned Reg = MO.getReg();
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if (!TargetRegisterInfo::isVirtualRegister(Reg))
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continue;
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if (MO.isDef())
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DstVirtualRegs.insert(Reg);
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else if (FoldAsLoadDefRegs.count(Reg)) {
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// Only handle the case where Reg is used in a single src operand.
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if (SrcVirtualRegToOp.find(Reg) != SrcVirtualRegToOp.end())
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SrcVirtualRegToOp.erase(Reg);
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else
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SrcVirtualRegToOp.insert(std::make_pair(Reg, i));
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}
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}
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for (DenseMap<unsigned, unsigned>::iterator SI = SrcVirtualRegToOp.begin(),
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SE = SrcVirtualRegToOp.end(); SI != SE; SI++) {
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// If the virtual register is updated by MI, we can't fold the load.
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if (DstVirtualRegs.count(SI->first)) continue;
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// Check whether we can fold the def into this operand.
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DefMI = MRI->getVRegDef(SI->first);
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assert(DefMI);
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bool SawStore = false;
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if (!DefMI->isSafeToMove(this, 0, SawStore))
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continue;
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SmallVector<unsigned, 8> Ops;
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Ops.push_back(SI->second);
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MachineInstr *FoldMI = foldMemoryOperand(MI, Ops, DefMI);
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if (!FoldMI) continue;
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FoldAsLoadDefRegs.erase(SI->first);
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return FoldMI;
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}
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return 0;
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}
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/// Expand2AddrUndef - Expand a single-def pseudo instruction to a two-addr
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/// instruction with two undef reads of the register being defined. This is
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/// used for mapping:
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@ -387,14 +387,6 @@ public:
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unsigned SrcReg2, int CmpMask, int CmpValue,
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const MachineRegisterInfo *MRI) const;
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/// optimizeLoadInstr - Try to remove the load by folding it to a register
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/// operand at the use. We fold the load instructions if and only if the
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/// def and use are in the same BB.
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virtual MachineInstr* optimizeLoadInstr(MachineInstr *MI,
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const MachineRegisterInfo *MRI,
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SmallSet<unsigned, 4> &FoldAsLoadDefRegs,
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MachineInstr *&DefMI) const;
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private:
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MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc,
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MachineFunction::iterator &MFI,
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@ -3,7 +3,8 @@
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define void @double_save(<4 x i32>* %Ap, <4 x i32>* %Bp, <8 x i32>* %P) nounwind ssp {
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entry:
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; CHECK: vmovaps
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; CHECK: vinsertf128 $1, ([[A0:%rdi|%rsi]]),
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; CHECK: vmovaps
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; CHECK: vinsertf128
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; CHECK: vmovups
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%A = load <4 x i32>* %Ap
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%B = load <4 x i32>* %Bp
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@ -34,7 +34,8 @@ entry:
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define double @squirt(double* %x) nounwind {
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entry:
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; CHECK: squirt:
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; CHECK: sqrtsd ([[A0]]), %xmm0
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; CHECK: movsd ([[A0]]), %xmm0
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; CHECK: sqrtsd %xmm0, %xmm0
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%z = load double* %x
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%t = call double @llvm.sqrt.f64(double %z)
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ret double %t
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@ -45,29 +45,3 @@ L:
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}
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; rdar://10554090
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; xor in exit block will be CSE'ed and load will be folded to xor in entry.
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define i1 @test3(i32* %P, i32* %Q) nounwind {
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; CHECK: test3:
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; CHECK: movl 8(%esp), %eax
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; CHECK: xorl (%eax),
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; CHECK: j
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; CHECK-NOT: xor
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entry:
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%0 = load i32* %P, align 4
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%1 = load i32* %Q, align 4
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%2 = xor i32 %0, %1
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%3 = and i32 %2, 65535
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%4 = icmp eq i32 %3, 0
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br i1 %4, label %exit, label %land.end
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exit:
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%shr.i.i19 = xor i32 %1, %0
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%5 = and i32 %shr.i.i19, 2147418112
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%6 = icmp eq i32 %5, 0
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br label %land.end
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land.end:
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%7 = phi i1 [ %6, %exit ], [ false, %entry ]
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ret i1 %7
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}
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@ -1,14 +1,11 @@
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; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s
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; RUN: llc < %s -march=x86 -mattr=+sse2 > %t
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; RUN: grep pcmpeqd %t | count 1
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; RUN: grep xor %t | count 1
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; RUN: not grep LCP %t
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define <2 x double> @foo() nounwind {
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ret <2 x double> bitcast (<2 x i64><i64 -1, i64 -1> to <2 x double>)
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; CHECK: foo:
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; CHECK: pcmpeqd %xmm{{[0-9]+}}, %xmm{{[0-9]+}}
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; CHECK-NEXT: ret
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}
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define <2 x double> @bar() nounwind {
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ret <2 x double> bitcast (<2 x i64><i64 0, i64 0> to <2 x double>)
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; CHECK: bar:
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; CHECK: xorps %xmm{{[0-9]+}}, %xmm{{[0-9]+}}
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; CHECK-NEXT: ret
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}
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@ -1,6 +1,6 @@
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -march=x86-64 -mcpu=nehalem -asm-verbose=false | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -march=x86-64 -mcpu=nehalem -asm-verbose=false -enable-unsafe-fp-math -enable-no-nans-fp-math | FileCheck -check-prefix=UNSAFE %s
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -march=x86-64 -mcpu=nehalem -asm-verbose=false -enable-no-nans-fp-math | FileCheck -check-prefix=FINITE %s
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; RUN: llc < %s -march=x86-64 -mcpu=nehalem -asm-verbose=false | FileCheck %s
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; RUN: llc < %s -march=x86-64 -mcpu=nehalem -asm-verbose=false -enable-unsafe-fp-math -enable-no-nans-fp-math | FileCheck -check-prefix=UNSAFE %s
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; RUN: llc < %s -march=x86-64 -mcpu=nehalem -asm-verbose=false -enable-no-nans-fp-math | FileCheck -check-prefix=FINITE %s
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; Some of these patterns can be matched as SSE min or max. Some of
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; then can be matched provided that the operands are swapped.
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@ -137,13 +137,16 @@ define double @ole_inverse(double %x, double %y) nounwind {
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}
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; CHECK: ogt_x:
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; CHECK-NEXT: maxsd LCP{{.*}}(%rip), %xmm0
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; CHECK-NEXT: xorp{{[sd]}} %xmm1, %xmm1
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; CHECK-NEXT: maxsd %xmm1, %xmm0
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; CHECK-NEXT: ret
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; UNSAFE: ogt_x:
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; UNSAFE-NEXT: maxsd LCP{{.*}}(%rip), %xmm0
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; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
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; UNSAFE-NEXT: maxsd %xmm1, %xmm0
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; UNSAFE-NEXT: ret
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; FINITE: ogt_x:
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; FINITE-NEXT: maxsd LCP{{.*}}(%rip), %xmm0
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; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
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; FINITE-NEXT: maxsd %xmm1, %xmm0
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; FINITE-NEXT: ret
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define double @ogt_x(double %x) nounwind {
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%c = fcmp ogt double %x, 0.000000e+00
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@ -152,13 +155,16 @@ define double @ogt_x(double %x) nounwind {
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}
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; CHECK: olt_x:
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; CHECK-NEXT: minsd LCP{{.*}}(%rip), %xmm0
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; CHECK-NEXT: xorp{{[sd]}} %xmm1, %xmm1
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; CHECK-NEXT: minsd %xmm1, %xmm0
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; CHECK-NEXT: ret
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; UNSAFE: olt_x:
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; UNSAFE-NEXT: minsd LCP{{.*}}(%rip), %xmm0
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; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
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; UNSAFE-NEXT: minsd %xmm1, %xmm0
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; UNSAFE-NEXT: ret
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; FINITE: olt_x:
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; FINITE-NEXT: minsd LCP{{.*}}(%rip), %xmm0
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; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
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; FINITE-NEXT: minsd %xmm1, %xmm0
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; FINITE-NEXT: ret
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define double @olt_x(double %x) nounwind {
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%c = fcmp olt double %x, 0.000000e+00
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@ -211,10 +217,12 @@ define double @olt_inverse_x(double %x) nounwind {
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; CHECK: oge_x:
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; CHECK: ucomisd %xmm1, %xmm0
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; UNSAFE: oge_x:
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; UNSAFE-NEXT: maxsd LCP{{.*}}(%rip), %xmm0
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; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
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; UNSAFE-NEXT: maxsd %xmm1, %xmm0
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; UNSAFE-NEXT: ret
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; FINITE: oge_x:
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; FINITE-NEXT: maxsd LCP{{.*}}(%rip), %xmm0
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; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
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; FINITE-NEXT: maxsd %xmm1, %xmm0
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; FINITE-NEXT: ret
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define double @oge_x(double %x) nounwind {
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%c = fcmp oge double %x, 0.000000e+00
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@ -225,10 +233,12 @@ define double @oge_x(double %x) nounwind {
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; CHECK: ole_x:
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; CHECK: ucomisd %xmm0, %xmm1
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; UNSAFE: ole_x:
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; UNSAFE-NEXT: minsd LCP{{.*}}(%rip), %xmm0
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; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
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; UNSAFE-NEXT: minsd %xmm1, %xmm0
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; UNSAFE-NEXT: ret
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; FINITE: ole_x:
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; FINITE-NEXT: minsd LCP{{.*}}(%rip), %xmm0
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; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
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; FINITE-NEXT: minsd %xmm1, %xmm0
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; FINITE-NEXT: ret
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define double @ole_x(double %x) nounwind {
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%c = fcmp ole double %x, 0.000000e+00
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@ -401,10 +411,12 @@ define double @ule_inverse(double %x, double %y) nounwind {
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; CHECK: ugt_x:
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; CHECK: ucomisd %xmm0, %xmm1
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; UNSAFE: ugt_x:
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; UNSAFE-NEXT: maxsd LCP{{.*}}(%rip), %xmm0
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; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
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; UNSAFE-NEXT: maxsd %xmm1, %xmm0
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; UNSAFE-NEXT: ret
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; FINITE: ugt_x:
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; FINITE-NEXT: maxsd LCP{{.*}}(%rip), %xmm0
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; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
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; FINITE-NEXT: maxsd %xmm1, %xmm0
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; FINITE-NEXT: ret
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define double @ugt_x(double %x) nounwind {
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%c = fcmp ugt double %x, 0.000000e+00
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@ -415,10 +427,12 @@ define double @ugt_x(double %x) nounwind {
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; CHECK: ult_x:
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; CHECK: ucomisd %xmm1, %xmm0
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; UNSAFE: ult_x:
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; UNSAFE-NEXT: minsd LCP{{.*}}(%rip), %xmm0
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; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
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; UNSAFE-NEXT: minsd %xmm1, %xmm0
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; UNSAFE-NEXT: ret
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; FINITE: ult_x:
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; FINITE-NEXT: minsd LCP{{.*}}(%rip), %xmm0
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; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
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; FINITE-NEXT: minsd %xmm1, %xmm0
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; FINITE-NEXT: ret
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define double @ult_x(double %x) nounwind {
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%c = fcmp ult double %x, 0.000000e+00
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@ -468,10 +482,12 @@ define double @ult_inverse_x(double %x) nounwind {
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; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0
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; CHECK-NEXT: ret
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; UNSAFE: uge_x:
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; UNSAFE-NEXT: maxsd LCP{{.*}}(%rip), %xmm0
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; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
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; UNSAFE-NEXT: maxsd %xmm1, %xmm0
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; UNSAFE-NEXT: ret
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; FINITE: uge_x:
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; FINITE-NEXT: maxsd LCP{{.*}}(%rip), %xmm0
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; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
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; FINITE-NEXT: maxsd %xmm1, %xmm0
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; FINITE-NEXT: ret
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define double @uge_x(double %x) nounwind {
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%c = fcmp uge double %x, 0.000000e+00
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@ -485,10 +501,12 @@ define double @uge_x(double %x) nounwind {
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; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0
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; CHECK-NEXT: ret
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; UNSAFE: ule_x:
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; UNSAFE-NEXT: minsd LCP{{.*}}(%rip), %xmm0
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; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
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; UNSAFE-NEXT: minsd %xmm1, %xmm0
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; UNSAFE-NEXT: ret
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; FINITE: ule_x:
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; FINITE-NEXT: minsd LCP{{.*}}(%rip), %xmm0
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; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
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; FINITE-NEXT: minsd %xmm1, %xmm0
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; FINITE-NEXT: ret
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define double @ule_x(double %x) nounwind {
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%c = fcmp ule double %x, 0.000000e+00
|
||||
@ -497,7 +515,8 @@ define double @ule_x(double %x) nounwind {
|
||||
}
|
||||
|
||||
; CHECK: uge_inverse_x:
|
||||
; CHECK-NEXT: minsd LCP{{.*}}(%rip), %xmm0
|
||||
; CHECK-NEXT: xorp{{[sd]}} %xmm1, %xmm1
|
||||
; CHECK-NEXT: minsd %xmm1, %xmm0
|
||||
; CHECK-NEXT: ret
|
||||
; UNSAFE: uge_inverse_x:
|
||||
; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
|
||||
@ -516,7 +535,8 @@ define double @uge_inverse_x(double %x) nounwind {
|
||||
}
|
||||
|
||||
; CHECK: ule_inverse_x:
|
||||
; CHECK-NEXT: maxsd LCP{{.*}}(%rip), %xmm0
|
||||
; CHECK-NEXT: xorp{{[sd]}} %xmm1, %xmm1
|
||||
; CHECK-NEXT: maxsd %xmm1, %xmm0
|
||||
; CHECK-NEXT: ret
|
||||
; UNSAFE: ule_inverse_x:
|
||||
; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
|
||||
|
@ -1,4 +1,4 @@
|
||||
; RUN: llc < %s -march=x86 -mcpu=yonah -mtriple=i386-apple-darwin | FileCheck %s
|
||||
; RUN: llc < %s -march=x86 -mcpu=yonah | FileCheck %s
|
||||
|
||||
|
||||
define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) nounwind {
|
||||
@ -14,8 +14,8 @@ define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) nounwind {
|
||||
define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) nounwind {
|
||||
; CHECK: test2:
|
||||
; CHECK: pcmp
|
||||
; CHECK: pxor LCP
|
||||
; CHECK: movdqa
|
||||
; CHECK: pcmp
|
||||
; CHECK: pxor
|
||||
; CHECK: ret
|
||||
%C = icmp sge <4 x i32> %A, %B
|
||||
%D = sext <4 x i1> %C to <4 x i32>
|
||||
|
Loading…
Reference in New Issue
Block a user