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AArch64/ARM64: add half as a storage type on ARM64.
This brings it into line with the AArch64 behaviour and should open the way for certain OpenCL features. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206286 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover
parent
380fa65d5d
commit
e8bc8a7d58
@ -84,6 +84,7 @@ ARM64TargetLowering::ARM64TargetLowering(ARM64TargetMachine &TM)
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// Set up the register classes.
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addRegisterClass(MVT::i32, &ARM64::GPR32allRegClass);
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addRegisterClass(MVT::i64, &ARM64::GPR64allRegClass);
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addRegisterClass(MVT::f16, &ARM64::FPR16RegClass);
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addRegisterClass(MVT::f32, &ARM64::FPR32RegClass);
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addRegisterClass(MVT::f64, &ARM64::FPR64RegClass);
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addRegisterClass(MVT::f128, &ARM64::FPR128RegClass);
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@ -370,10 +371,13 @@ ARM64TargetLowering::ARM64TargetLowering(ARM64TargetMachine &TM)
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setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
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setLoadExtAction(ISD::EXTLOAD, MVT::f80, Expand);
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setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Expand);
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setTruncStoreAction(MVT::f32, MVT::f16, Expand);
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setTruncStoreAction(MVT::f64, MVT::f32, Expand);
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setTruncStoreAction(MVT::f64, MVT::f16, Expand);
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setTruncStoreAction(MVT::f128, MVT::f80, Expand);
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setTruncStoreAction(MVT::f128, MVT::f64, Expand);
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setTruncStoreAction(MVT::f128, MVT::f32, Expand);
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setTruncStoreAction(MVT::f128, MVT::f16, Expand);
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setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
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// Indexed loads and stores are supported.
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for (unsigned im = (unsigned)ISD::PRE_INC;
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@ -3396,28 +3396,28 @@ class BaseFPConversion<bits<2> type, bits<2> opcode, RegisterClass dstType,
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multiclass FPConversion<string asm> {
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// Double-precision to Half-precision
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let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
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def HDr : BaseFPConversion<0b01, 0b11, FPR16, FPR64, asm, []>;
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def HDr : BaseFPConversion<0b01, 0b11, FPR16, FPR64, asm,
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[(set FPR16:$Rd, (fround FPR64:$Rn))]>;
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// Double-precision to Single-precision
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def SDr : BaseFPConversion<0b01, 0b00, FPR32, FPR64, asm,
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[(set FPR32:$Rd, (fround FPR64:$Rn))]>;
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// Half-precision to Double-precision
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let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
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def DHr : BaseFPConversion<0b11, 0b01, FPR64, FPR16, asm, []>;
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def DHr : BaseFPConversion<0b11, 0b01, FPR64, FPR16, asm,
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[(set FPR64:$Rd, (fextend FPR16:$Rn))]>;
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// Half-precision to Single-precision
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let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
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def SHr : BaseFPConversion<0b11, 0b00, FPR32, FPR16, asm, []>;
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def SHr : BaseFPConversion<0b11, 0b00, FPR32, FPR16, asm,
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[(set FPR32:$Rd, (fextend FPR16:$Rn))]>;
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// Single-precision to Double-precision
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def DSr : BaseFPConversion<0b00, 0b01, FPR64, FPR32, asm,
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[(set FPR64:$Rd, (fextend FPR32:$Rn))]>;
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// Single-precision to Half-precision
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let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
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def HSr : BaseFPConversion<0b00, 0b11, FPR16, FPR32, asm, []>;
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def HSr : BaseFPConversion<0b00, 0b11, FPR16, FPR32, asm,
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[(set FPR16:$Rd, (fround FPR32:$Rn))]>;
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}
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//---
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@ -1022,7 +1022,7 @@ def LDRXro : Load64RO<0b11, 0, 0b01, GPR64, "ldr",
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def LDRBro : Load8RO<0b00, 1, 0b01, FPR8, "ldr",
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[(set FPR8:$Rt, (load ro_indexed8:$addr))]>;
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def LDRHro : Load16RO<0b01, 1, 0b01, FPR16, "ldr",
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[(set FPR16:$Rt, (load ro_indexed16:$addr))]>;
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[(set (f16 FPR16:$Rt), (load ro_indexed16:$addr))]>;
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def LDRSro : Load32RO<0b10, 1, 0b01, FPR32, "ldr",
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[(set (f32 FPR32:$Rt), (load ro_indexed32:$addr))]>;
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def LDRDro : Load64RO<0b11, 1, 0b01, FPR64, "ldr",
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@ -1132,7 +1132,7 @@ def LDRWui : LoadUI<0b10, 0, 0b01, GPR32, am_indexed32, "ldr",
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def LDRBui : LoadUI<0b00, 1, 0b01, FPR8, am_indexed8, "ldr",
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[(set FPR8:$Rt, (load am_indexed8:$addr))]>;
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def LDRHui : LoadUI<0b01, 1, 0b01, FPR16, am_indexed16, "ldr",
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[(set FPR16:$Rt, (load am_indexed16:$addr))]>;
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[(set (f16 FPR16:$Rt), (load am_indexed16:$addr))]>;
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def LDRSui : LoadUI<0b10, 1, 0b01, FPR32, am_indexed32, "ldr",
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[(set (f32 FPR32:$Rt), (load am_indexed32:$addr))]>;
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def LDRDui : LoadUI<0b11, 1, 0b01, FPR64, am_indexed64, "ldr",
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@ -1261,7 +1261,7 @@ def LDURWi : LoadUnscaled<0b10, 0, 0b01, GPR32, am_unscaled32, "ldur",
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def LDURBi : LoadUnscaled<0b00, 1, 0b01, FPR8, am_unscaled8, "ldur",
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[(set FPR8:$Rt, (load am_unscaled8:$addr))]>;
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def LDURHi : LoadUnscaled<0b01, 1, 0b01, FPR16, am_unscaled16, "ldur",
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[(set FPR16:$Rt, (load am_unscaled16:$addr))]>;
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[(set (f16 FPR16:$Rt), (load am_unscaled16:$addr))]>;
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def LDURSi : LoadUnscaled<0b10, 1, 0b01, FPR32, am_unscaled32, "ldur",
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[(set (f32 FPR32:$Rt), (load am_unscaled32:$addr))]>;
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def LDURDi : LoadUnscaled<0b11, 1, 0b01, FPR64, am_unscaled64, "ldur",
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@ -1575,7 +1575,7 @@ def : Pat<(truncstorei32 GPR64:$Rt, ro_indexed32:$addr),
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def STRBro : Store8RO<0b00, 1, 0b00, FPR8, "str",
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[(store FPR8:$Rt, ro_indexed8:$addr)]>;
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def STRHro : Store16RO<0b01, 1, 0b00, FPR16, "str",
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[(store FPR16:$Rt, ro_indexed16:$addr)]>;
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[(store (f16 FPR16:$Rt), ro_indexed16:$addr)]>;
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def STRSro : Store32RO<0b10, 1, 0b00, FPR32, "str",
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[(store (f32 FPR32:$Rt), ro_indexed32:$addr)]>;
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def STRDro : Store64RO<0b11, 1, 0b00, FPR64, "str",
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@ -1623,7 +1623,7 @@ def STRWui : StoreUI<0b10, 0, 0b00, GPR32, am_indexed32, "str",
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def STRBui : StoreUI<0b00, 1, 0b00, FPR8, am_indexed8, "str",
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[(store FPR8:$Rt, am_indexed8:$addr)]>;
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def STRHui : StoreUI<0b01, 1, 0b00, FPR16, am_indexed16, "str",
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[(store FPR16:$Rt, am_indexed16:$addr)]>;
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[(store (f16 FPR16:$Rt), am_indexed16:$addr)]>;
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def STRSui : StoreUI<0b10, 1, 0b00, FPR32, am_indexed32, "str",
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[(store (f32 FPR32:$Rt), am_indexed32:$addr)]>;
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def STRDui : StoreUI<0b11, 1, 0b00, FPR64, am_indexed64, "str",
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@ -1686,7 +1686,7 @@ def STURWi : StoreUnscaled<0b10, 0, 0b00, GPR32, am_unscaled32, "stur",
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def STURBi : StoreUnscaled<0b00, 1, 0b00, FPR8, am_unscaled8, "stur",
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[(store FPR8:$Rt, am_unscaled8:$addr)]>;
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def STURHi : StoreUnscaled<0b01, 1, 0b00, FPR16, am_unscaled16, "stur",
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[(store FPR16:$Rt, am_unscaled16:$addr)]>;
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[(store (f16 FPR16:$Rt), am_unscaled16:$addr)]>;
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def STURSi : StoreUnscaled<0b10, 1, 0b00, FPR32, am_unscaled32, "stur",
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[(store (f32 FPR32:$Rt), am_unscaled32:$addr)]>;
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def STURDi : StoreUnscaled<0b11, 1, 0b00, FPR64, am_unscaled64, "stur",
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@ -368,7 +368,7 @@ def Q31 : ARM64Reg<31, "q31", [D31], ["v31", ""]>, DwarfRegAlias<B31>;
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def FPR8 : RegisterClass<"ARM64", [untyped], 8, (sequence "B%u", 0, 31)> {
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let Size = 8;
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}
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def FPR16 : RegisterClass<"ARM64", [untyped], 16, (sequence "H%u", 0, 31)> {
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def FPR16 : RegisterClass<"ARM64", [f16], 16, (sequence "H%u", 0, 31)> {
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let Size = 16;
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}
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def FPR32 : RegisterClass<"ARM64", [f32, i32], 32,(sequence "S%u", 0, 31)>;
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@ -1,4 +1,5 @@
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; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
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; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-apple-ios7.0 | FileCheck %s
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@varhalf = global half 0.0
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@varfloat = global float 0.0
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